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260b08aed4
Refactor acp driver pm ops to support SoundWire interface. When SoundWire configuration is enabled, In case of ClockStopMode, DSP soft reset should be applied and for rest of the scenarios acp init/deinit sequence should be invoked. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://msgid.link/r/20240129055147.1493853-14-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
110 lines
3.7 KiB
C
110 lines
3.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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*/
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#ifndef _ACP_DSP_IP_OFFSET_H
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#define _ACP_DSP_IP_OFFSET_H
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/* Registers from ACP_DMA_0 block */
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#define ACP_DMA_CNTL_0 0x00
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#define ACP_DMA_DSCR_STRT_IDX_0 0x20
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#define ACP_DMA_DSCR_CNT_0 0x40
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#define ACP_DMA_PRIO_0 0x60
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#define ACP_DMA_CUR_DSCR_0 0x80
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#define ACP_DMA_ERR_STS_0 0xC0
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#define ACP_DMA_DESC_BASE_ADDR 0xE0
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#define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4
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#define ACP_DMA_CH_STS 0xE8
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#define ACP_DMA_CH_GROUP 0xEC
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#define ACP_DMA_CH_RST_STS 0xF0
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/* Registers from ACP_DSP_0 block */
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#define ACP_DSP0_RUNSTALL 0x414
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/* Registers from ACP_AXI2AXIATU block */
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC00
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC04
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC08
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0xC10
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0xC14
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0xC18
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0xC1C
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0xC28
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0xC2C
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0xC30
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0xC34
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0xC38
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0xC3C
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#define ACPAXI2AXI_ATU_CTRL 0xC40
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#define ACP_SOFT_RESET 0x1000
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#define ACP_CONTROL 0x1004
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#define ACP3X_I2S_PIN_CONFIG 0x1400
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#define ACP5X_I2S_PIN_CONFIG 0x1400
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#define ACP6X_I2S_PIN_CONFIG 0x1440
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/* Registers offsets from ACP_PGFSM block */
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#define ACP3X_PGFSM_BASE 0x141C
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#define ACP5X_PGFSM_BASE 0x1424
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#define ACP6X_PGFSM_BASE 0x1024
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#define PGFSM_CONTROL_OFFSET 0x0
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#define PGFSM_STATUS_OFFSET 0x4
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#define ACP3X_CLKMUX_SEL 0x1424
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#define ACP5X_CLKMUX_SEL 0x142C
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#define ACP6X_CLKMUX_SEL 0x102C
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/* Registers from ACP_INTR block */
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#define ACP3X_EXT_INTR_STAT 0x1808
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#define ACP5X_EXT_INTR_STAT 0x1808
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#define ACP6X_EXTERNAL_INTR_ENB 0x1A00
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#define ACP6X_EXTERNAL_INTR_CNTL 0x1A04
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#define ACP6X_EXT_INTR_STAT 0x1A0C
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#define ACP6X_EXT_INTR_STAT1 0x1A10
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#define ACP3X_DSP_SW_INTR_BASE 0x1814
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#define ACP5X_DSP_SW_INTR_BASE 0x1814
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#define ACP6X_DSP_SW_INTR_BASE 0x1808
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#define DSP_SW_INTR_CNTL_OFFSET 0x0
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#define DSP_SW_INTR_STAT_OFFSET 0x4
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#define DSP_SW_INTR_TRIG_OFFSET 0x8
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#define ACP_ERROR_STATUS 0x18C4
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#define ACP3X_AXI2DAGB_SEM_0 0x1880
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#define ACP5X_AXI2DAGB_SEM_0 0x1884
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#define ACP6X_AXI2DAGB_SEM_0 0x1874
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/* ACP common registers to report errors related to I2S & SoundWire interfaces */
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#define ACP_SW0_I2S_ERROR_REASON 0x18B4
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#define ACP_SW1_I2S_ERROR_REASON 0x1A50
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/* Registers from ACP_SHA block */
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#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70
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#define ACP_SHA_DMA_CMD 0x1CB0
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#define ACP_SHA_MSG_LENGTH 0x1CB4
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#define ACP_SHA_DMA_STRT_ADDR 0x1CB8
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#define ACP_SHA_DMA_DESTINATION_ADDR 0x1CBC
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#define ACP_SHA_DMA_CMD_STS 0x1CC0
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#define ACP_SHA_DMA_ERR_STATUS 0x1CC4
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#define ACP_SHA_TRANSFER_BYTE_CNT 0x1CC8
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#define ACP_SHA_DMA_INCLUDE_HDR 0x1CCC
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#define ACP_SHA_PSP_ACK 0x1C74
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#define ACP_SCRATCH_REG_0 0x10000
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#define ACP6X_DSP_FUSION_RUNSTALL 0x0644
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/* Cache window registers */
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#define ACP_DSP0_CACHE_OFFSET0 0x0420
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#define ACP_DSP0_CACHE_SIZE0 0x0424
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#define ACP_SW0_EN 0x3000
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#define ACP_SW1_EN 0x3C00
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#endif
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