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f4cc33e78b
Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located. The base of custom interrupt number is set
to 256.
To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as a private data.
Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node to
enable the use of custom local interrupt source.
e.g.,
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
...
cpu0-intc: interrupt-controller {
#interrupt-cells = <0x01>;
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20240222083946.3977135-4-peterlin@andestech.com
19 lines
446 B
C
19 lines
446 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2023 Andes Technology Corporation
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*/
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#ifndef __ANDES_IRQ_H
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#define __ANDES_IRQ_H
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/* Andes PMU irq number */
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#define ANDES_RV_IRQ_PMOVI 18
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#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
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#define ANDES_SLI_CAUSE_BASE 256
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/* Andes PMU related registers */
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#define ANDES_CSR_SLIE 0x9c4
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#define ANDES_CSR_SLIP 0x9c5
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#define ANDES_CSR_SCOUNTEROF 0x9d4
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#endif /* __ANDES_IRQ_H */
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