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b70cb1a21a
In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.
The nocache option is removed from following clocks:
- vclk2_sel
- vclk2_input
- vclk2_div
- vclk2
- vclk_div1
- vclk2_div2_en
- vclk2_div4_en
- vclk2_div6_en
- vclk2_div12_en
- vclk2_div2
- vclk2_div4
- vclk2_div6
- vclk2_div12
- cts_encl_sel
vclk2 and vclk2_div uses the newly introduced vclk regmap driver
to handle the enable and reset bits.
In order to set a rate on cts_encl via the vclk2 clock path,
the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
to keep CCF from selection a parent.
The parents of cts_encl_sel & vclk2_sel are expected to be defined
in DT or manually set by the display driver at some point.
The following clock scheme is to be used for DSI:
xtal
\_ gp0_pll_dco
\_ gp0_pll
|- vclk2_sel
| \_ vclk2_input
| \_ vclk2_div
| \_ vclk2
| \_ vclk2_div1
| \_ cts_encl_sel
| \_ cts_encl -> to VPU LCD Encoder
|- mipi_dsi_pxclk_sel
\_ mipi_dsi_pxclk_div
\_ mipi_dsi_pxclk -> to DSI controller
The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table
in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input.
The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the
DSI bitclock is the reference base clock to calculate the vclk2_div value
when pixel clock is set on the cts_encl endpoint.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
178 lines
4.9 KiB
Plaintext
178 lines
4.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "Clock support for Amlogic platforms"
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depends on ARCH_MESON || COMPILE_TEST
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config COMMON_CLK_MESON_REGMAP
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tristate
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select REGMAP
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config COMMON_CLK_MESON_DUALDIV
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_MPLL
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_PHASE
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_PLL
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_SCLK_DIV
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_VID_PLL_DIV
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_VCLK
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON_CLKC_UTILS
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tristate
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config COMMON_CLK_MESON_AO_CLKC
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tristate
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_CLKC_UTILS
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select RESET_CONTROLLER
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config COMMON_CLK_MESON_EE_CLKC
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tristate
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_CLKC_UTILS
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config COMMON_CLK_MESON_CPU_DYNDIV
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tristate
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select COMMON_CLK_MESON_REGMAP
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config COMMON_CLK_MESON8B
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bool "Meson8 SoC Clock controller support"
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depends on ARM
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_CLKC_UTILS
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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select MFD_SYSCON
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select RESET_CONTROLLER
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help
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Support for the clock controller on AmLogic S802 (Meson8),
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S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
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want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_GXBB
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tristate "GXBB and GXL SoC clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_VID_PLL_DIV
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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select COMMON_CLK_MESON_AO_CLKC
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select COMMON_CLK_MESON_EE_CLKC
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select MFD_SYSCON
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help
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Support for the clock controller on AmLogic S905 devices, aka gxbb.
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Say Y if you want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_AXG
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tristate "AXG SoC clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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select COMMON_CLK_MESON_AO_CLKC
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select COMMON_CLK_MESON_EE_CLKC
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select MFD_SYSCON
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help
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Support for the clock controller on AmLogic A113D devices, aka axg.
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Say Y if you want peripherals and CPU frequency scaling to work.
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config COMMON_CLK_AXG_AUDIO
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tristate "Meson AXG Audio Clock Controller Driver"
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depends on ARM64
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_PHASE
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select COMMON_CLK_MESON_SCLK_DIV
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select COMMON_CLK_MESON_CLKC_UTILS
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select REGMAP_MMIO
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help
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Support for the audio clock controller on AmLogic A113D devices,
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aka axg, Say Y if you want audio subsystem to work.
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config COMMON_CLK_A1_PLL
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tristate "Amlogic A1 SoC PLL controller support"
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depends on ARM64
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_CLKC_UTILS
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select COMMON_CLK_MESON_PLL
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help
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Support for the PLL clock controller on Amlogic A113L based
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device, A1 SoC Family. Say Y if you want A1 PLL clock controller
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to work.
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config COMMON_CLK_A1_PERIPHERALS
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tristate "Amlogic A1 SoC Peripherals clock controller support"
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depends on ARM64
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_CLKC_UTILS
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help
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Support for the Peripherals clock controller on Amlogic A113L based
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device, A1 SoC Family. Say Y if you want A1 Peripherals clock
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controller to work.
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config COMMON_CLK_G12A
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tristate "G12 and SM1 SoC clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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select COMMON_CLK_MESON_AO_CLKC
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select COMMON_CLK_MESON_EE_CLKC
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select COMMON_CLK_MESON_CPU_DYNDIV
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select COMMON_CLK_MESON_VID_PLL_DIV
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select COMMON_CLK_MESON_VCLK
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select MFD_SYSCON
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help
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Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
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devices, aka g12a. Say Y if you want peripherals to work.
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config COMMON_CLK_S4_PLL
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tristate "S4 SoC PLL clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_CLKC_UTILS
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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select COMMON_CLK_MESON_REGMAP
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help
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Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices,
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AKA S4. Say Y if you want the board to work, because PLLs are the parent of
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most peripherals.
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config COMMON_CLK_S4_PERIPHERALS
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tristate "S4 SoC peripherals clock controllers support"
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depends on ARM64
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default y
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select COMMON_CLK_MESON_CLKC_UTILS
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_VID_PLL_DIV
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help
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Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
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devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
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endmenu
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