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_PAGE_USER is used to select the zone. Today zone 0 is kernel and zone 1 is user. To implement _PAGE_NONE, _PAGE_USER is cleared, leading to no access for user but kernel still has access to the page so it's possible for a user application to write in that page by using a kernel function as trampoline. What is really wanted is to have user rights on pages below TASK_SIZE and no user rights on pages above TASK_SIZE. Use zones for that. There are 16 zones so lets use the 4 upper address bits to set the zone and declare zone rights based on TASK_SIZE. Then drop _PAGE_USER and reuse it as _PAGE_READ that will be checked in Data TLB miss handler. That will properly handle PAGE_NONE for both kernel and user. In addition, it partially implements execute-only right. The implementation won't be complete because once a TLB has been loaded via the Instruction TLB miss handler, it will be possible to read the page. But at least it can't be read unless it is executed first. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/2a13e3ba8a5dec43143cc1f9a91ec71ea1529f3c.1695659959.git.christophe.leroy@csgroup.eu
162 lines
4.1 KiB
C
162 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* This file contains the routines for initializing the MMU
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* on the 4xx series of chips.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/stddef.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/memblock.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/mmu.h>
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#include <linux/uaccess.h>
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#include <asm/smp.h>
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#include <asm/bootx.h>
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#include <asm/machdep.h>
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#include <asm/setup.h>
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#include <mm/mmu_decl.h>
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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int i;
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unsigned long zpr;
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/*
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* The Zone Protection Register (ZPR) defines how protection will
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* be applied to every page which is a member of a given zone.
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* The zone index bits (of ZSEL) in the PTE are used for software
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* indicators. We use the 4 upper bits of virtual address to select
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* the zone. We set all zones above TASK_SIZE to zero, allowing
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* only kernel access as indicated in the PTE. For zones below
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* TASK_SIZE, we set a 01 binary (a value of 10 will not work)
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* to allow user access as indicated in the PTE. This also allows
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* kernel access as indicated in the PTE.
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*/
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for (i = 0, zpr = 0; i < TASK_SIZE >> 28; i++)
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zpr |= 1 << (30 - i * 2);
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mtspr(SPRN_ZPR, zpr);
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flush_instruction_cache();
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/*
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* Set up the real-mode cache parameters for the exception vector
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* handlers (which are run in real-mode).
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*/
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mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
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/*
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* Cache instruction and data space where the exception
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* vectors and the kernel live in real-mode.
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*/
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mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
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mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
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}
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#define LARGE_PAGE_SIZE_16M (1<<24)
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#define LARGE_PAGE_SIZE_4M (1<<22)
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unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
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{
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unsigned long v, s, mapped;
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phys_addr_t p;
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v = KERNELBASE;
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p = 0;
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s = total_lowmem;
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if (IS_ENABLED(CONFIG_KFENCE))
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return 0;
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if (debug_pagealloc_enabled())
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return 0;
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if (strict_kernel_rwx_enabled())
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return 0;
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while (s >= LARGE_PAGE_SIZE_16M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
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pmdp = pmd_off_k(v);
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*pmdp++ = __pmd(val);
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*pmdp++ = __pmd(val);
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*pmdp++ = __pmd(val);
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*pmdp++ = __pmd(val);
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v += LARGE_PAGE_SIZE_16M;
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p += LARGE_PAGE_SIZE_16M;
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s -= LARGE_PAGE_SIZE_16M;
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}
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while (s >= LARGE_PAGE_SIZE_4M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
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pmdp = pmd_off_k(v);
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*pmdp = __pmd(val);
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v += LARGE_PAGE_SIZE_4M;
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p += LARGE_PAGE_SIZE_4M;
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s -= LARGE_PAGE_SIZE_4M;
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}
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mapped = total_lowmem - s;
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/* If the size of RAM is not an exact power of two, we may not
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* have covered RAM in its entirety with 16 and 4 MiB
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* pages. Consequently, restrict the top end of RAM currently
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* allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
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* coverage with normal-sized pages (or other reasons) do not
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* attempt to allocate outside the allowed range.
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*/
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memblock_set_current_limit(mapped);
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return mapped;
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}
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void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/* We don't currently support the first MEMBLOCK not mapping 0
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* physical on those processors
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*/
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BUG_ON(first_memblock_base != 0);
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/* 40x can only access 16MB at the moment (see head_40x.S) */
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memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
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}
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