Nikola Cornij d68a745417 drm/amd/display: Clear FEC_READY shadow register if DPCD write fails ... [why] As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow register should be cleared and the internal FEC stat should be set to 'not ready'. This is to make sure HW settings will be consistent with FEC_READY state on the RX. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-07-18 14:27:25 -05:00
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amdgpu_dm	drm/amd/display: add functionality to get pipe CRC source.	2019-07-18 14:18:09 -05:00
dc	drm/amd/display: Clear FEC_READY shadow register if DPCD write fails	2019-07-18 14:27:25 -05:00
include	drm/amd/display:Use Pixel clock in 100Hz units for HDMI Audio wall clock DTO	2019-07-18 14:18:09 -05:00
modules	drm/amd/display: Optimize gamma calculations	2019-07-18 14:27:25 -05:00
Kconfig	drm/amd/display: Add drm_audio_component support to amdgpu_dm	2019-07-11 14:37:24 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00