Nicholas Kazlauskas d374d3b493 drm/amd/display: Fix out of bounds access on DNC31 stream encoder regs ... [Why] During dcn31_stream_encoder_create, if PHYC/D get remapped to F/G on B0 then we'll index 5 or 6 into a array of length 5 - leading to an access violation on some configs during device creation. [How] Software won't be touching PHYF/PHYG directly, so just extend the array to cover all possible engine IDs. Even if it does by try to access one of these registers by accident the offset will be 0 and we'll get a warning during the access. Fixes: 2fe9a0e117 ("drm/amd/display: Fix DCN3 B0 DP Alt Mapping") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-07 13:12:27 -05:00
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drm	drm/amd/display: Fix out of bounds access on DNC31 stream encoder regs	2021-12-07 13:12:27 -05:00
host1x	gpu: host1x: Plug potential memory leak	2021-09-16 18:06:52 +02:00
ipu-v3	media: i.MX6: Support 16-bit BT.1120 video input	2021-10-19 08:08:38 +01:00
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vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
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