Matthew Brost d35ca60087 drm/i915/guc: Ensure H2G buffer updates visible before tail update ... Ensure H2G buffer updates are visible before descriptor tail updates by inserting a barrier between the H2G buffer update and the tail. The barrier is simple wmb() for SMEM and is register write for LMEM. This is needed if more than 1 H2G can be inflight at once. If this barrier is not inserted it is possible the descriptor tail update is scene by the GuC before H2G buffer update which results in the GuC reading a corrupt H2G value. This can bring down the H2G channel among other bad things. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210603051630.2635-16-matthew.brost@intel.com		2021-06-04 10:39:04 +02:00
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drm	drm/i915/guc: Ensure H2G buffer updates visible before tail update	2021-06-04 10:39:04 +02:00
host1x	gpu: host1x: Add early init and late exit callbacks	2021-03-31 17:42:14 +02:00
ipu-v3	gpu: ipu-v3: Add Rec.709 limited range support to DP	2021-05-10 17:20:29 +02:00
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vga	vgaarb: Use ACPI HID name to find integrated GPU	2021-05-20 14:55:56 -04:00
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