Yash Shah 00a5bf3a8c RISC-V: Add PCIe I/O BAR memory mapping ... For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux, we need to establish a reserved memory region for them, so that drivers that wish to use the legacy I/O BARs can issue reads and writes against a memory region that is mapped to the host PCIe controller's I/O BAR mapping. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-10-28 10:43:32 -07:00
..
asm	RISC-V: Add PCIe I/O BAR memory mapping	2019-10-28 10:43:32 -07:00
uapi/asm	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00