Rob Herring 9af865d95b dt-bindings: riscv: Fix CPU schema errors ... Fix the errors in the RiscV CPU DT schema: Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5'] Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node and RiscV requires it in /cpus node, so make it disallowed in cpu nodes. Fixes: 4fd669a8c4 ("dt-bindings: riscv: convert cpu binding to json-schema") Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: linux-riscv@lists.infradead.org Acked-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Rob Herring <robh@kernel.org>		2019-10-23 14:42:44 -05:00
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cpus.yaml	dt-bindings: riscv: Fix CPU schema errors	2019-10-23 14:42:44 -05:00
sifive-l2-cache.txt	RISC-V: Add DT documentation for SiFive L2 Cache Controller	2019-05-16 20:42:13 -07:00
sifive.yaml	dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed board	2019-08-08 16:05:38 -07:00