Ramesh Errabolu d25e35bc26 drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain ... MMIO/DOORBELL BOs encode control data and should be pinned in GTT domain before enabling PCIe connected peer devices in accessing it Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-11-22 14:45:01 -05:00
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acp
amdgpu	drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain	2021-11-22 14:45:01 -05:00
amdkfd	drm/amdkfd: replace asic_family with asic_type	2021-11-17 17:10:01 -05:00
display	drm/amd/display: Reduce dmesg error to a debug print	2021-11-22 14:45:01 -05:00
include	drm/amdkfd: remove kgd_dev declaration and initialization	2021-11-17 16:58:03 -05:00
pm	drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs	2021-11-17 17:10:10 -05:00