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0bfbc914d9
* Support for byte/half-word compare-and-exchange, emulated via LR/SC
loops.
* Support for Rust.
* Support for Zihintpause in hwprobe.
* Support for the PR_RISCV_SET_ICACHE_FLUSH_CTX prctl().
* Support for lockless lockrefs.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmZN/hcTHHBhbG1lckBk
YWJiZWx0LmNvbQAKCRAuExnzX7sYiVrGEACUT3gsbTx1q7fa11iQNxOjVkpl66Qn
7+kI+V9xt5+GuH2EjJk6AsSNHPKeQ8totbSTA8AZjINFvgVjXslN+DPpcjCFKvnh
NN5/Lyd64X0PZMsxGWlN9SHTFWf2b7lalCnY51BlX/IpBbHWc/no9XUsPSVixx6u
9q+JoS3D1DDV92nGcA/UK9ICCsDcf4omWgZW7KbjnVWnuY9jt4ctTy11jtF2RM9R
Z9KAWh0RqPzjz0vNbBBf9Iw7E4jt/Px6HDYPfZAiE2dVsCTHjdsC7TcGRYXzKt6F
4q9zg8kzwvUG5GaBl7/XprXO1vaeOUmPcTVoE7qlRkSdkknRH/iBz1P4hk+r0fze
f+h5ZUV/oJP7vDb+vHm/BExtGufgLuJ2oMA2Bp9qI17EMcMsGiRMt7DsBMEafWDk
bNrFcJdqqYBz6HxfTwzNH5ErxfS/59PuwYl913BTSOH//raCZCFXOfyrSICH7qXd
UFOLLmBpMuApLa8ayFeI9Mp3flWfbdQHR52zLRLiUvlpWNEDKrNQN417juVwTXF0
DYkjJDhFPLfFOr/sJBboftOMOUdA9c/CJepY9o4kPvBXUvPtRHN1jdXDNSCVDZRb
nErnsJ9rv0PzfxQU7Xjhd2QmCMeMlbCQDpXAKKETyyimpTbgF33rovN0i5ixX3m4
KG6RvKDubOzZdA==
=YLoD
-----END PGP SIGNATURE-----
Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Add byte/half-word compare-and-exchange, emulated via LR/SC loops
- Support for Rust
- Support for Zihintpause in hwprobe
- Add PR_RISCV_SET_ICACHE_FLUSH_CTX prctl()
- Support lockless lockrefs
* tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800
riscv: select ARCH_HAS_FAST_MULTIPLIER
riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required
riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_init
riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabled
riscv: mm: Always use an ASID to flush mm contexts
riscv: mm: Preserve global TLB entries when switching contexts
riscv: mm: Make asid_bits a local variable
riscv: mm: Use a fixed layout for the MM context ID
riscv: mm: Introduce cntx2asid/cntx2version helper macros
riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
riscv: mm: Combine the SMP and UP TLB flush code
riscv: Only send remote fences when some other CPU is online
riscv: mm: Broadcast kernel TLB flushes only when needed
riscv: Use IPIs for remote cache/TLB flushes by default
riscv: Factor out page table TLB synchronization
riscv: Flush the instruction cache during SMP bringup
riscv: hwprobe: export Zihintpause ISA extension
riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code
...
77 lines
2.7 KiB
C
77 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright 2023 Rivos, Inc
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*/
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#ifndef _UAPI_ASM_HWPROBE_H
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#define _UAPI_ASM_HWPROBE_H
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#include <linux/types.h>
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/*
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* Interface for probing hardware capabilities from userspace, see
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* Documentation/arch/riscv/hwprobe.rst for more information.
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*/
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struct riscv_hwprobe {
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__s64 key;
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__u64 value;
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};
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#define RISCV_HWPROBE_KEY_MVENDORID 0
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#define RISCV_HWPROBE_KEY_MARCHID 1
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#define RISCV_HWPROBE_KEY_MIMPID 2
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#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
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#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
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#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
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#define RISCV_HWPROBE_IMA_FD (1 << 0)
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#define RISCV_HWPROBE_IMA_C (1 << 1)
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#define RISCV_HWPROBE_IMA_V (1 << 2)
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#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
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#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
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#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
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#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
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#define RISCV_HWPROBE_EXT_ZBC (1 << 7)
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#define RISCV_HWPROBE_EXT_ZBKB (1 << 8)
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#define RISCV_HWPROBE_EXT_ZBKC (1 << 9)
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#define RISCV_HWPROBE_EXT_ZBKX (1 << 10)
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#define RISCV_HWPROBE_EXT_ZKND (1 << 11)
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#define RISCV_HWPROBE_EXT_ZKNE (1 << 12)
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#define RISCV_HWPROBE_EXT_ZKNH (1 << 13)
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#define RISCV_HWPROBE_EXT_ZKSED (1 << 14)
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#define RISCV_HWPROBE_EXT_ZKSH (1 << 15)
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#define RISCV_HWPROBE_EXT_ZKT (1 << 16)
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#define RISCV_HWPROBE_EXT_ZVBB (1 << 17)
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#define RISCV_HWPROBE_EXT_ZVBC (1 << 18)
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#define RISCV_HWPROBE_EXT_ZVKB (1 << 19)
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#define RISCV_HWPROBE_EXT_ZVKG (1 << 20)
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#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
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#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
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#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
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#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
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#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
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#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
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#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
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#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
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#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
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#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
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#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
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#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
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#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
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#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
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#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
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#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
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#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
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#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
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#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
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#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
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/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
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/* Flags */
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#define RISCV_HWPROBE_WHICH_CPUS (1 << 0)
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#endif
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