Duncan Ma cfa1e7f8a7 drm/amd/display: Fix OTG H timing reset for dcn314 ... [Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-08-29 17:45:27 -04:00
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amdgpu_dm	drm/amd/display: Remove redundant check in atomic_check	2022-08-25 13:35:17 -04:00
dc	drm/amd/display: Fix OTG H timing reset for dcn314	2022-08-29 17:45:27 -04:00
dmub	drm/amd/display: [FW Promotion] Release 0.0.130.0	2022-08-25 13:19:29 -04:00
include	drm/amd/display: add chip revision to DCN32	2022-08-16 18:09:25 -04:00
modules	drm/amd/display: Fix HDMI VSIF V3 incorrect issue	2022-08-10 15:12:13 -04:00
Kconfig	drm/amd/display: Enable building new display engine with KCOV enabled	2022-07-18 16:42:38 -04:00
Makefile
TODO