Sergio Paracuellos ebe7e788ee MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base' ... By default MIPS architecture use function 'set_io_port_base()' to set the virtual address of the first IO port. This function at the end sets variable 'mips_io_port_base' with the desired address. To align things and allow to change first IO port location address for PCI, set PCI_IOBASE definition as 'mips_io_port_base'. Fixes: 222b27713d ("MIPS: ralink: Define PCI_IOBASE") Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210925203224.10419-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2021-10-05 12:36:25 +02:00
..
mt7620	MIPS: remove cpu_has_64bit_addresses	2020-04-19 16:08:29 +02:00
mt7621	MIPS: remove cpu_has_64bit_addresses	2020-04-19 16:08:29 +02:00
rt288x	MIPS: remove cpu_has_64bit_addresses	2020-04-19 16:08:29 +02:00
rt305x	MIPS: remove cpu_has_64bit_addresses	2020-04-19 16:08:29 +02:00
rt3883	MIPS: remove cpu_has_64bit_addresses	2020-04-19 16:08:29 +02:00
irq.h	MIPS: Add header files reference with path prefix	2020-03-19 13:12:27 +01:00
mt7620.h	pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file	2021-06-07 09:17:47 +02:00
mt7621.h	MIPS: ralink: mt7621: add memory detection support	2021-03-29 11:18:54 +02:00
ralink_regs.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
rt288x.h	pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file	2021-06-07 09:17:48 +02:00
rt305x.h	pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file	2021-06-07 09:17:47 +02:00
rt3883.h	pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file	2021-06-07 09:17:47 +02:00
spaces.h	MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base'	2021-10-05 12:36:25 +02:00