Like Xu cb1d220da0 KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register ... If we run the following perf command in an AMD Milan guest: perf stat \ -e cpu/event=0x1d0/ \ -e cpu/event=0x1c7/ \ -e cpu/umask=0x1f,event=0x18e/ \ -e cpu/umask=0x7,event=0x18e/ \ -e cpu/umask=0x18,event=0x18e/ \ ./workload dmesg will report a #GP warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx. This is because according to APM (Revision: 4.03) Figure 13-7, the bits [35:32] of AMD PerfEvtSeln register is a part of the event select encoding, which extends the EVENT_SELECT field from 8 bits to 12 bits. Opportunistically update pmu->reserved_bits for reserved bit 19. Reported-by: Jim Mattson <jmattson@google.com> Fixes: ca724305a2 ("KVM: x86/vPMU: Implement AMD vPMU code for KVM") Signed-off-by: Like Xu <likexu@tencent.com> Message-Id: <20211118130320.95997-1-likexu@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2021-12-02 04:11:50 -05:00
..
avic.c	KVM: fix avic_set_running for preemptable kernels	2021-11-30 07:40:48 -05:00
nested.c	nSVM: Check for reserved encodings of TLB_CONTROL in nested VMCB	2021-10-01 03:44:57 -04:00
pmu.c	KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register	2021-12-02 04:11:50 -05:00
sev.c	KVM: SEV: accept signals in sev_lock_two_vms	2021-11-30 03:54:15 -05:00
svm_onhyperv.c	KVM: SVM: hyper-v: Direct Virtual Flush support	2021-06-17 13:09:38 -04:00
svm_onhyperv.h	KVM: SVM: delay svm_vcpu_init_msrpm after svm->vmcb is initialized	2021-07-27 16:59:00 -04:00
svm_ops.h	x86/kvm: Always inline vmload() / vmsave()	2021-09-15 15:51:45 +02:00
svm.c	KVM: x86: check PIR even for vCPUs with disabled APICv	2021-11-30 03:52:39 -05:00
svm.h	KVM: SEV: Prohibit migration of a VM that has mirrors	2021-11-30 03:54:14 -05:00
vmenter.S	KVM/SVM: Move vmenter.S exception fixups out of line	2021-03-15 04:43:56 -04:00