Justin Chen 0e9b114132 soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS) ... This commit adds support for the Broadcom STB S2/S3/S5 suspend states on MIPS based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY - DDR memory controller and arbiter - control processor The final steps of the suspend execute in cache and there is is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wait loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>		2017-09-25 11:47:14 -07:00
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aon_defs.h
Makefile
pm-arm.c
pm-mips.c
pm.h
s2-arm.S
s2-mips.S
s3-mips.S