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591de9fb73
Add mu5/6 for i.MX8QXP/QM, these two mu will be used for communicating with general purpose Cortex-M4 cores. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
70 lines
1.2 KiB
Plaintext
70 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019-2020 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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&lsio_gpio0 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio1 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio2 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio3 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio4 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio5 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio6 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio7 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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};
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&lsio_mu0 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu1 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu2 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu3 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu4 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu5 {
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compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu6 {
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compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu13 {
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compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
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};
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