mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-12-24 14:49:47 +00:00
ed4643521e
After a somewhat quiet 5.17 release, the size of the DT changes
is a bit larger again. There are nine new SoC that get added,
all of them related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the
LG Nexus 5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs,
along with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC losely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added all
over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91, Allwinner,
i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)
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Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"After a somewhat quiet 5.17 release, the size of the DT changes is a
bit larger again. There are nine new SoC that get added, all of them
related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added
all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic:
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno:
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar:
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)"
* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
arm64: dts: n5x: drop invalid property and fix edac node name
arm64: dts: fsd: Add the MCT support
arm64: dts: stingray: Fix spi clock name
arm64: dts: ns2: Fix spi clock name
ARM: dts: rockchip: Update regulator name for PX3
ARM: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
ARM: dts: at91: sama7g5: Add NAND support
ARM: dts: at91: sama7g5: add eic node
ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
arm64: dts: lg: align pl330 node name with dtschema
arm64: dts: lg: add dma-cells to pl330 node
arm64: dts: juno: align pl330 node name with dtschema
arm64: dts: broadcom: Fix sata nodename
arm64: dts: n5x: add sdr edac support
arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
dt-bindings: usb: dwc2: add disable-over-current
...
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "imx8mm-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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cpu_pd_wait: cpu-pd-wait {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010033>;
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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};
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};
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A53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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nvmem-cells = <&cpu_speed_grade>;
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nvmem-cell-names = "speed_grade";
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cpu-idle-states = <&cpu_pd_wait>;
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#cooling-cells = <2>;
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};
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A53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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#cooling-cells = <2>;
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};
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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#cooling-cells = <2>;
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};
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A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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#cooling-cells = <2>;
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};
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A53_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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};
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a53_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <850000>;
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opp-supported-hw = <0xe>, <0x7>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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opp-1600000000 {
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opp-hz = /bits/ 64 <1600000000>;
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opp-microvolt = <950000>;
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opp-supported-hw = <0xc>, <0x7>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1000000>;
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opp-supported-hw = <0x8>, <0x3>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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clk_ext2: clock-ext2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext2";
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};
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clk_ext3: clock-ext3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext3";
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};
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency= <133000000>;
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clock-output-names = "clk_ext4";
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8000000>;
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arm,no-tick-in-suspend;
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu>;
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trips {
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cpu_alert0: trip0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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usbphynop1: usbphynop1 {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
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assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
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clock-names = "main_clk";
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};
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usbphynop2: usbphynop2 {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
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assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
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clock-names = "main_clk";
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};
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soc@0 {
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compatible = "fsl,imx8mm-soc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x3e000000>;
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dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
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nvmem-cells = <&imx8mm_uid>;
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nvmem-cell-names = "soc_unique_id";
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aips1: bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x30000000 0x400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x30000000 0x30000000 0x400000>;
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spba2: spba-bus@30000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30000000 0x100000>;
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ranges;
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sai1: sai@30010000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
|
reg = <0x30010000 0x10000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
|
|
<&clk IMX8MM_CLK_SAI1_ROOT>,
|
|
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai2: sai@30020000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
|
reg = <0x30020000 0x10000>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
|
|
<&clk IMX8MM_CLK_SAI2_ROOT>,
|
|
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai3: sai@30030000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
|
reg = <0x30030000 0x10000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
|
|
<&clk IMX8MM_CLK_SAI3_ROOT>,
|
|
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai5: sai@30050000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
|
reg = <0x30050000 0x10000>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
|
|
<&clk IMX8MM_CLK_SAI5_ROOT>,
|
|
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai6: sai@30060000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
|
reg = <0x30060000 0x10000>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
|
|
<&clk IMX8MM_CLK_SAI6_ROOT>,
|
|
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
micfil: audio-controller@30080000 {
|
|
compatible = "fsl,imx8mm-micfil";
|
|
reg = <0x30080000 0x10000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_PDM_IPG>,
|
|
<&clk IMX8MM_CLK_PDM_ROOT>,
|
|
<&clk IMX8MM_AUDIO_PLL1_OUT>,
|
|
<&clk IMX8MM_AUDIO_PLL2_OUT>,
|
|
<&clk IMX8MM_CLK_EXT3>;
|
|
clock-names = "ipg_clk", "ipg_clk_app",
|
|
"pll8k", "pll11k", "clkext3";
|
|
dmas = <&sdma2 24 25 0x80000000>;
|
|
dma-names = "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif1: spdif@30090000 {
|
|
compatible = "fsl,imx35-spdif";
|
|
reg = <0x30090000 0x10000>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
|
|
<&clk IMX8MM_CLK_24M>, /* rxtx0 */
|
|
<&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
|
|
<&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
|
|
<&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
|
|
<&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
|
|
<&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
|
|
<&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
|
|
<&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
|
|
<&clk IMX8MM_CLK_DUMMY>; /* spba */
|
|
clock-names = "core", "rxtx0",
|
|
"rxtx1", "rxtx2",
|
|
"rxtx3", "rxtx4",
|
|
"rxtx5", "rxtx6",
|
|
"rxtx7", "spba";
|
|
dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpio1: gpio@30200000 {
|
|
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30200000 0x10000>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 10 30>;
|
|
};
|
|
|
|
gpio2: gpio@30210000 {
|
|
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30210000 0x10000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 40 21>;
|
|
};
|
|
|
|
gpio3: gpio@30220000 {
|
|
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30220000 0x10000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 61 26>;
|
|
};
|
|
|
|
gpio4: gpio@30230000 {
|
|
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30230000 0x10000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 87 32>;
|
|
};
|
|
|
|
gpio5: gpio@30240000 {
|
|
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30240000 0x10000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 119 30>;
|
|
};
|
|
|
|
tmu: tmu@30260000 {
|
|
compatible = "fsl,imx8mm-tmu";
|
|
reg = <0x30260000 0x10000>;
|
|
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
wdog1: watchdog@30280000 {
|
|
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30280000 0x10000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog2: watchdog@30290000 {
|
|
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30290000 0x10000>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog3: watchdog@302a0000 {
|
|
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
|
|
reg = <0x302a0000 0x10000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma2: dma-controller@302c0000 {
|
|
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
|
reg = <0x302c0000 0x10000>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
|
|
<&clk IMX8MM_CLK_SDMA2_ROOT>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
|
};
|
|
|
|
sdma3: dma-controller@302b0000 {
|
|
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
|
reg = <0x302b0000 0x10000>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
|
|
<&clk IMX8MM_CLK_SDMA3_ROOT>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
|
};
|
|
|
|
iomuxc: pinctrl@30330000 {
|
|
compatible = "fsl,imx8mm-iomuxc";
|
|
reg = <0x30330000 0x10000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@30340000 {
|
|
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
|
|
reg = <0x30340000 0x10000>;
|
|
};
|
|
|
|
ocotp: efuse@30350000 {
|
|
compatible = "fsl,imx8mm-ocotp", "syscon";
|
|
reg = <0x30350000 0x10000>;
|
|
clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
|
|
/* For nvmem subnodes */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
imx8mm_uid: unique-id@410 {
|
|
reg = <0x4 0x8>;
|
|
};
|
|
|
|
cpu_speed_grade: speed-grade@10 {
|
|
reg = <0x10 4>;
|
|
};
|
|
|
|
fec_mac_address: mac-address@90 {
|
|
reg = <0x90 6>;
|
|
};
|
|
};
|
|
|
|
anatop: anatop@30360000 {
|
|
compatible = "fsl,imx8mm-anatop", "syscon";
|
|
reg = <0x30360000 0x10000>;
|
|
};
|
|
|
|
snvs: snvs@30370000 {
|
|
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
|
|
reg = <0x30370000 0x10000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap = <&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
|
|
clock-names = "snvs-rtc";
|
|
};
|
|
|
|
snvs_pwrkey: snvs-powerkey {
|
|
compatible = "fsl,sec-v4.0-pwrkey";
|
|
regmap = <&snvs>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
|
|
clock-names = "snvs-pwrkey";
|
|
linux,keycode = <KEY_POWER>;
|
|
wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clk: clock-controller@30380000 {
|
|
compatible = "fsl,imx8mm-ccm";
|
|
reg = <0x30380000 0x10000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
|
<&clk_ext3>, <&clk_ext4>;
|
|
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
|
"clk_ext3", "clk_ext4";
|
|
assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
|
|
<&clk IMX8MM_CLK_A53_CORE>,
|
|
<&clk IMX8MM_CLK_NOC>,
|
|
<&clk IMX8MM_CLK_AUDIO_AHB>,
|
|
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
|
|
<&clk IMX8MM_SYS_PLL3>,
|
|
<&clk IMX8MM_VIDEO_PLL1>,
|
|
<&clk IMX8MM_AUDIO_PLL1>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
|
|
<&clk IMX8MM_ARM_PLL_OUT>,
|
|
<&clk IMX8MM_SYS_PLL3_OUT>,
|
|
<&clk IMX8MM_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <0>, <0>, <0>,
|
|
<400000000>,
|
|
<400000000>,
|
|
<750000000>,
|
|
<594000000>,
|
|
<393216000>;
|
|
};
|
|
|
|
src: reset-controller@30390000 {
|
|
compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
|
|
reg = <0x30390000 0x10000>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@303a0000 {
|
|
compatible = "fsl,imx8mm-gpc";
|
|
reg = <0x303a0000 0x10000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
pgc {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pgc_hsiomix: power-domain@0 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
|
|
clocks = <&clk IMX8MM_CLK_USB_BUS>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
|
|
};
|
|
|
|
pgc_pcie: power-domain@1 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_PCIE>;
|
|
power-domains = <&pgc_hsiomix>;
|
|
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
|
|
};
|
|
|
|
pgc_otg1: power-domain@2 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_OTG1>;
|
|
power-domains = <&pgc_hsiomix>;
|
|
};
|
|
|
|
pgc_otg2: power-domain@3 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_OTG2>;
|
|
power-domains = <&pgc_hsiomix>;
|
|
};
|
|
|
|
pgc_gpumix: power-domain@4 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
|
|
clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
|
<&clk IMX8MM_CLK_GPU_AHB>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
|
|
<&clk IMX8MM_CLK_GPU_AHB>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
|
|
<&clk IMX8MM_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <800000000>, <400000000>;
|
|
};
|
|
|
|
pgc_gpu: power-domain@5 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_GPU>;
|
|
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
|
|
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
|
<&clk IMX8MM_CLK_GPU2D_ROOT>,
|
|
<&clk IMX8MM_CLK_GPU3D_ROOT>;
|
|
resets = <&src IMX8MQ_RESET_GPU_RESET>;
|
|
power-domains = <&pgc_gpumix>;
|
|
};
|
|
|
|
pgc_vpumix: power-domain@6 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
|
|
clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
|
|
};
|
|
|
|
pgc_vpu_g1: power-domain@7 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
|
|
};
|
|
|
|
pgc_vpu_g2: power-domain@8 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
|
|
};
|
|
|
|
pgc_vpu_h1: power-domain@9 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
|
|
};
|
|
|
|
pgc_dispmix: power-domain@10 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
|
|
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
|
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
|
|
<&clk IMX8MM_CLK_DISP_APB>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
|
|
<&clk IMX8MM_SYS_PLL1_800M>;
|
|
assigned-clock-rates = <500000000>, <200000000>;
|
|
};
|
|
|
|
pgc_mipi: power-domain@11 {
|
|
#power-domain-cells = <0>;
|
|
reg = <IMX8MM_POWER_DOMAIN_MIPI>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
aips2: bus@30400000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x30400000 0x400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x30400000 0x30400000 0x400000>;
|
|
|
|
pwm1: pwm@30660000 {
|
|
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30660000 0x10000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
|
|
<&clk IMX8MM_CLK_PWM1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@30670000 {
|
|
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30670000 0x10000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
|
|
<&clk IMX8MM_CLK_PWM2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@30680000 {
|
|
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30680000 0x10000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
|
|
<&clk IMX8MM_CLK_PWM3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@30690000 {
|
|
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30690000 0x10000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
|
|
<&clk IMX8MM_CLK_PWM4_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
system_counter: timer@306a0000 {
|
|
compatible = "nxp,sysctr-timer";
|
|
reg = <0x306a0000 0x20000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc_24m>;
|
|
clock-names = "per";
|
|
};
|
|
};
|
|
|
|
aips3: bus@30800000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x30800000 0x400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x30800000 0x30800000 0x400000>,
|
|
<0x8000000 0x8000000 0x10000000>;
|
|
|
|
spba1: spba-bus@30800000 {
|
|
compatible = "fsl,spba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x30800000 0x100000>;
|
|
ranges;
|
|
|
|
ecspi1: spi@30820000 {
|
|
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30820000 0x10000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
|
|
<&clk IMX8MM_CLK_ECSPI1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: spi@30830000 {
|
|
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30830000 0x10000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
|
|
<&clk IMX8MM_CLK_ECSPI2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi3: spi@30840000 {
|
|
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30840000 0x10000>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
|
|
<&clk IMX8MM_CLK_ECSPI3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@30860000 {
|
|
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
|
reg = <0x30860000 0x10000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
|
|
<&clk IMX8MM_CLK_UART1_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@30880000 {
|
|
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
|
reg = <0x30880000 0x10000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
|
|
<&clk IMX8MM_CLK_UART3_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@30890000 {
|
|
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
|
reg = <0x30890000 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
|
|
<&clk IMX8MM_CLK_UART2_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
crypto: crypto@30900000 {
|
|
compatible = "fsl,sec-v4.0";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x30900000 0x40000>;
|
|
ranges = <0 0x30900000 0x40000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_AHB>,
|
|
<&clk IMX8MM_CLK_IPG_ROOT>;
|
|
clock-names = "aclk", "ipg";
|
|
|
|
sec_jr0: jr@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr2: jr@3000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x3000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
i2c1: i2c@30a20000 {
|
|
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a20000 0x10000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@30a30000 {
|
|
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a30000 0x10000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@30a40000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a40000 0x10000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@30a50000 {
|
|
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x30a50000 0x10000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@30a60000 {
|
|
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
|
reg = <0x30a60000 0x10000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
|
|
<&clk IMX8MM_CLK_UART4_ROOT>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mu: mailbox@30aa0000 {
|
|
compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
|
|
reg = <0x30aa0000 0x10000>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_MU_ROOT>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
usdhc1: mmc@30b40000 {
|
|
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
|
reg = <0x30b40000 0x10000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
|
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MM_CLK_USDHC1_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: mmc@30b50000 {
|
|
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
|
reg = <0x30b50000 0x10000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
|
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MM_CLK_USDHC2_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: mmc@30b60000 {
|
|
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
|
reg = <0x30b60000 0x10000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
|
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
|
<&clk IMX8MM_CLK_USDHC3_ROOT>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexspi: spi@30bb0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nxp,imx8mm-fspi";
|
|
reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
|
|
reg-names = "fspi_base", "fspi_mmap";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
|
|
<&clk IMX8MM_CLK_QSPI_ROOT>;
|
|
clock-names = "fspi_en", "fspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma1: dma-controller@30bd0000 {
|
|
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
|
reg = <0x30bd0000 0x10000>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
|
|
<&clk IMX8MM_CLK_AHB>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
|
};
|
|
|
|
fec1: ethernet@30be0000 {
|
|
compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
|
reg = <0x30be0000 0x10000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
|
|
<&clk IMX8MM_CLK_ENET1_ROOT>,
|
|
<&clk IMX8MM_CLK_ENET_TIMER>,
|
|
<&clk IMX8MM_CLK_ENET_REF>,
|
|
<&clk IMX8MM_CLK_ENET_PHY_REF>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
|
|
<&clk IMX8MM_CLK_ENET_TIMER>,
|
|
<&clk IMX8MM_CLK_ENET_REF>,
|
|
<&clk IMX8MM_CLK_ENET_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
|
|
<&clk IMX8MM_SYS_PLL2_100M>,
|
|
<&clk IMX8MM_SYS_PLL2_125M>,
|
|
<&clk IMX8MM_SYS_PLL2_50M>;
|
|
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
|
|
fsl,num-tx-queues = <3>;
|
|
fsl,num-rx-queues = <3>;
|
|
nvmem-cells = <&fec_mac_address>;
|
|
nvmem-cell-names = "mac-address";
|
|
fsl,stop-mode = <&gpr 0x10 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|
|
aips4: bus@32c00000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x32c00000 0x400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x32c00000 0x32c00000 0x400000>;
|
|
|
|
csi: csi@32e20000 {
|
|
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
|
|
reg = <0x32e20000 0x1000>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
|
|
clock-names = "mclk";
|
|
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
|
|
status = "disabled";
|
|
|
|
port {
|
|
csi_in: endpoint {
|
|
remote-endpoint = <&imx8mm_mipi_csi_out>;
|
|
};
|
|
};
|
|
};
|
|
|
|
disp_blk_ctrl: blk-ctrl@32e28000 {
|
|
compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
|
|
reg = <0x32e28000 0x100>;
|
|
power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
|
|
<&pgc_dispmix>, <&pgc_mipi>,
|
|
<&pgc_mipi>;
|
|
power-domain-names = "bus", "csi-bridge",
|
|
"lcdif", "mipi-dsi",
|
|
"mipi-csi";
|
|
clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
|
|
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
|
<&clk IMX8MM_CLK_CSI1_ROOT>,
|
|
<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
|
|
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
|
<&clk IMX8MM_CLK_DISP_ROOT>,
|
|
<&clk IMX8MM_CLK_DSI_CORE>,
|
|
<&clk IMX8MM_CLK_DSI_PHY_REF>,
|
|
<&clk IMX8MM_CLK_CSI1_CORE>,
|
|
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
|
|
clock-names = "csi-bridge-axi","csi-bridge-apb",
|
|
"csi-bridge-core", "lcdif-axi",
|
|
"lcdif-apb", "lcdif-pix",
|
|
"dsi-pclk", "dsi-ref",
|
|
"csi-aclk", "csi-pclk";
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
mipi_csi: mipi-csi@32e30000 {
|
|
compatible = "fsl,imx8mm-mipi-csi2";
|
|
reg = <0x32e30000 0x1000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
|
|
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
|
|
<&clk IMX8MM_SYS_PLL2_1000M>;
|
|
clock-frequency = <333000000>;
|
|
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
|
<&clk IMX8MM_CLK_CSI1_ROOT>,
|
|
<&clk IMX8MM_CLK_CSI1_PHY_REF>,
|
|
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
|
|
clock-names = "pclk", "wrap", "phy", "axi";
|
|
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
imx8mm_mipi_csi_out: endpoint {
|
|
remote-endpoint = <&csi_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
usbotg1: usb@32e40000 {
|
|
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
|
|
reg = <0x32e40000 0x200>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
|
|
clock-names = "usb1_ctrl_root_clk";
|
|
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
|
|
phys = <&usbphynop1>;
|
|
fsl,usbmisc = <&usbmisc1 0>;
|
|
power-domains = <&pgc_otg1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc1: usbmisc@32e40200 {
|
|
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
|
|
#index-cells = <1>;
|
|
reg = <0x32e40200 0x200>;
|
|
};
|
|
|
|
usbotg2: usb@32e50000 {
|
|
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
|
|
reg = <0x32e50000 0x200>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
|
|
clock-names = "usb1_ctrl_root_clk";
|
|
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
|
|
phys = <&usbphynop2>;
|
|
fsl,usbmisc = <&usbmisc2 0>;
|
|
power-domains = <&pgc_otg2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc2: usbmisc@32e50200 {
|
|
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
|
|
#index-cells = <1>;
|
|
reg = <0x32e50200 0x200>;
|
|
};
|
|
|
|
pcie_phy: pcie-phy@32f00000 {
|
|
compatible = "fsl,imx8mm-pcie-phy";
|
|
reg = <0x32f00000 0x10000>;
|
|
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
|
|
clock-names = "ref";
|
|
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
|
|
assigned-clock-rates = <100000000>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
|
|
resets = <&src IMX8MQ_RESET_PCIEPHY>;
|
|
reset-names = "pciephy";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dma_apbh: dma-controller@33000000 {
|
|
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
|
|
reg = <0x33000000 0x2000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
|
|
#dma-cells = <1>;
|
|
dma-channels = <4>;
|
|
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
|
|
};
|
|
|
|
gpmi: nand-controller@33002000{
|
|
compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
|
|
reg-names = "gpmi-nand", "bch";
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "bch";
|
|
clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
|
|
<&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
|
|
clock-names = "gpmi_io", "gpmi_bch_apb";
|
|
dmas = <&dma_apbh 0>;
|
|
dma-names = "rx-tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie0: pcie@33800000 {
|
|
compatible = "fsl,imx8mm-pcie";
|
|
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
|
|
reg-names = "dbi", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
|
|
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
|
|
num-lanes = <1>;
|
|
num-viewport = <4>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,max-link-speed = <2>;
|
|
linux,pci-domain = <0>;
|
|
power-domains = <&pgc_pcie>;
|
|
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
|
|
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
|
|
reset-names = "apps", "turnoff";
|
|
phys = <&pcie_phy>;
|
|
phy-names = "pcie-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu_3d: gpu@38000000 {
|
|
compatible = "vivante,gc";
|
|
reg = <0x38000000 0x8000>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
|
|
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
|
<&clk IMX8MM_CLK_GPU3D_ROOT>,
|
|
<&clk IMX8MM_CLK_GPU3D_ROOT>;
|
|
clock-names = "reg", "bus", "core", "shader";
|
|
assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
|
|
<&clk IMX8MM_GPU_PLL_OUT>;
|
|
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
|
|
assigned-clock-rates = <0>, <1000000000>;
|
|
power-domains = <&pgc_gpu>;
|
|
};
|
|
|
|
gpu_2d: gpu@38008000 {
|
|
compatible = "vivante,gc";
|
|
reg = <0x38008000 0x8000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
|
|
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
|
<&clk IMX8MM_CLK_GPU2D_ROOT>;
|
|
clock-names = "reg", "bus", "core";
|
|
assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
|
|
<&clk IMX8MM_GPU_PLL_OUT>;
|
|
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
|
|
assigned-clock-rates = <0>, <1000000000>;
|
|
power-domains = <&pgc_gpu>;
|
|
};
|
|
|
|
vpu_g1: video-codec@38300000 {
|
|
compatible = "nxp,imx8mm-vpu-g1";
|
|
reg = <0x38300000 0x10000>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
|
|
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
|
|
};
|
|
|
|
vpu_g2: video-codec@38310000 {
|
|
compatible = "nxp,imx8mq-vpu-g2";
|
|
reg = <0x38310000 0x10000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
|
|
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
|
|
};
|
|
|
|
vpu_blk_ctrl: blk-ctrl@38330000 {
|
|
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
|
|
reg = <0x38330000 0x100>;
|
|
power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
|
|
<&pgc_vpu_g2>, <&pgc_vpu_h1>;
|
|
power-domain-names = "bus", "g1", "g2", "h1";
|
|
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
|
|
<&clk IMX8MM_CLK_VPU_G2_ROOT>,
|
|
<&clk IMX8MM_CLK_VPU_H1_ROOT>;
|
|
clock-names = "g1", "g2", "h1";
|
|
assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
|
|
<&clk IMX8MM_CLK_VPU_G2>;
|
|
assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
|
|
<&clk IMX8MM_VPU_PLL_OUT>;
|
|
assigned-clock-rates = <600000000>,
|
|
<600000000>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@38800000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x38800000 0x10000>, /* GIC Dist */
|
|
<0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ddrc: memory-controller@3d400000 {
|
|
compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
|
|
reg = <0x3d400000 0x400000>;
|
|
clock-names = "core", "pll", "alt", "apb";
|
|
clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
|
|
<&clk IMX8MM_DRAM_PLL>,
|
|
<&clk IMX8MM_CLK_DRAM_ALT>,
|
|
<&clk IMX8MM_CLK_DRAM_APB>;
|
|
};
|
|
|
|
ddr-pmu@3d800000 {
|
|
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
|
|
reg = <0x3d800000 0x400000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|