Yu-ting Shen cab5dec425 drm/amd/display: limit display clock to 100MHz to avoid FIFO error ... [Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-25 11:10:08 -05:00
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amdgpu_dm	drm/amd/display: Add DMUB firmware state debugfs	2020-02-25 11:05:57 -05:00
dc	drm/amd/display: limit display clock to 100MHz to avoid FIFO error	2020-02-25 11:10:08 -05:00
dmub	drm/amd/display: Add driver support for enabling PSR on DMCUB	2020-02-25 11:09:06 -05:00
include	drm/amd/display: Fix RV2 Variant Detection	2020-02-25 11:09:12 -05:00
modules	drm/amd/display: Fix HDMI repeater authentication	2020-02-25 11:04:16 -05:00
Kconfig	amdgpu: Enable initial DCN support on POWER	2019-12-18 16:09:05 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00