mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2026-01-07 00:38:57 +00:00
New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants
of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST
+ Reference boards for stm32mp15
- ST Ericsson
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl4+kmIPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3WIIP/2Nbbe0AKMbWK4tr53UffdZ+/voO5zp/M6Eq
6yeUmbMYSLqq4N3jRpFGoEnIPUVccLKffIi5EjdFygVl3C6D54O4IhgHPh4jBvWJ
wr+vKpbNX6wekI2/LoHRnNTKz4xX2RcmW7eI/2RGvJgL3/7jaXm9g9QqZHf1Ne0T
/JHEkl2xkgbIvgQ8UCTB38VHQKe2FdC6bzGRDttBJOv5NJvQScZSqyS91iiB0IWe
uYMSI9A/k2LMgTDA+QD6uaL4U3RO2fxmMOTQI72QKLgLePaoUyG844R3RGsU1axc
n9MiazspS6V/c3zsfJAUU6MQivD0arBWJrkb8CCVDIW6Az8QhR/0HnkvcwUXPd35
tzhCX0idJb3z7TKVx+SWuFDnmVma9g9nplEPcQc2MSaQxnwG0Xulxgsp1Pq69xZ5
mh+k065Xdk4J7MENNQpBtlpfUUX8f9doIz7zA4LpLTQEXBdgy1TtPMdMrzdbhH5u
T/a29u8CubJjhBoZ70P6LabvtMVOmZYhi46hhdEylfINYnOKOQq7uokJU6SV5Vha
cYZFuNzhAk2PsujDpoYQPY1eqjoKbzheBRtunNJ9or+ALWO/NRXq+9QdUW4CnSXo
xy3dXMj2vJ4B+3XRuxEcFhS/L9nJsf5YyPs8xjaYmcy1BMcH2mJz3e8s0+ayUk1t
QjU6sWVt
=Upyw
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all
variants of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of
db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner:
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic:
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip:
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST:
+ Reference boards for stm32mp15
- ST Ericsson:
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP:
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm:
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits)
dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml
arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera
arm64: dts: ti: k3-am65-main Add CAL node
arm64: dts: ti: k3-j721e-main: Add McASP nodes
arm64: dts: ti: k3-am654-main: Add McASP nodes
arm64: dts: ti: k3-j721e: DMA support
arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss
arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation
arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
arm64: dts: ti: k3-am65: DMA support
arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss
arm64: dts: ti: k3-am65-main: Correct main NAVSS representation
ARM: dts: aspeed: rainier: Add UCD90320 power sequencer
ARM: dts: aspeed: rainier: Switch PSUs to unknown version
arm64: dts: rockchip: Kill off "simple-panel" compatibles
ARM: dts: rockchip: Kill off "simple-panel" compatibles
arm64: dts: rockchip: rename dwmmc node names to mmc
ARM: dts: rockchip: rename dwmmc node names to mmc
arm64: dts: exynos: Rename Samsung and Exynos to lowercase
arm64: dts: uniphier: add reset-names to NAND controller node
...
194 lines
5.7 KiB
Plaintext
194 lines
5.7 KiB
Plaintext
Atmel system registers
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Chipid required properties:
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- compatible: Should be "atmel,sama5d2-chipid"
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- reg : Should contain registers location and length
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PIT Timer required properties:
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- compatible: Should be "atmel,at91sam9260-pit"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt for the PIT which is the IRQ line
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shared across all System Controller members.
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PIT64B Timer required properties:
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- compatible: Should be "microchip,sam9x60-pit64b"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt for PIT64B timer
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- clocks: Should contain the available clock sources for PIT64B timer.
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System Timer (ST) required properties:
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- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt for the ST which is the IRQ line
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shared across all System Controller members.
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- clocks: phandle to input clock.
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Its subnodes can be:
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- watchdog: compatible should be "atmel,at91rm9200-wdt"
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RSTC Reset Controller required properties:
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- compatible: Should be "atmel,<chip>-rstc".
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<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
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it also can be "microchip,sam9x60-rstc"
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- reg: Should contain registers location and length
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- clocks: phandle to input clock.
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Example:
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rstc@fffffd00 {
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compatible = "atmel,at91sam9260-rstc";
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reg = <0xfffffd00 0x10>;
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clocks = <&clk32k>;
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};
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RAMC SDRAM/DDR Controller required properties:
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- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
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"atmel,at91sam9260-sdramc",
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"atmel,at91sam9g45-ddramc",
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"atmel,sama5d3-ddramc",
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"microchip,sam9x60-ddramc"
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- reg: Should contain registers location and length
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Examples:
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ramc0: ramc@ffffe800 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe800 0x200>;
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};
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SHDWC Shutdown Controller
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required properties:
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- compatible: Should be "atmel,<chip>-shdwc".
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<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
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- reg: Should contain registers location and length
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- clocks: phandle to input clock.
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optional properties:
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- atmel,wakeup-mode: String, operation mode of the wakeup mode.
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Supported values are: "none", "high", "low", "any".
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- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
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optional at91sam9260 properties:
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
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optional at91sam9rl properties:
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- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
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optional at91sam9x5 properties:
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- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
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Example:
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shdwc@fffffd10 {
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compatible = "atmel,at91sam9260-shdwc";
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reg = <0xfffffd10 0x10>;
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clocks = <&clk32k>;
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};
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SHDWC SAMA5D2-Compatible Shutdown Controller
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1) shdwc node
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required properties:
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- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
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- reg: should contain registers location and length
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- clocks: phandle to input clock.
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- #address-cells: should be one. The cell is the wake-up input index.
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- #size-cells: should be zero.
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optional properties:
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- debounce-delay-us: minimum wake-up inputs debouncer period in
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microseconds. It's usually a board-related property.
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- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
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optional microchip,sam9x60-shdwc properties:
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
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The node contains child nodes for each wake-up input that the platform uses.
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2) input nodes
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Wake-up input nodes are usually described in the "board" part of the Device
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Tree. Note also that input 0 is linked to the wake-up pin and is frequently
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used.
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Required properties:
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- reg: should contain the wake-up input index [0 - 15].
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Optional properties:
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- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
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by the child, forces the wake-up of the core power supply on a high level.
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The default is to be active low.
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Example:
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On the SoC side:
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shdwc@f8048010 {
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compatible = "atmel,sama5d2-shdwc";
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reg = <0xf8048010 0x10>;
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clocks = <&clk32k>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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};
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On the board side:
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shdwc@f8048010 {
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debounce-delay-us = <976>;
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input@0 {
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reg = <0>;
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};
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input@1 {
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reg = <1>;
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atmel,wakeup-active-high;
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};
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};
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Special Function Registers (SFR)
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Special Function Registers (SFR) manage specific aspects of the integrated
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memory, bridge implementations, processor and other functionality not controlled
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elsewhere.
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required properties:
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- compatible: Should be "atmel,<chip>-sfr", "syscon" or
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"atmel,<chip>-sfrbu", "syscon"
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<chip> can be "sama5d3", "sama5d4" or "sama5d2".
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It also can be "microchip,sam9x60-sfr", "syscon".
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- reg: Should contain registers location and length
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sfr@f0038000 {
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compatible = "atmel,sama5d3-sfr", "syscon";
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reg = <0xf0038000 0x60>;
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};
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Security Module (SECUMOD)
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The Security Module macrocell provides all necessary secure functions to avoid
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voltage, temperature, frequency and mechanical attacks on the chip. It also
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embeds secure memories that can be scrambled.
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The Security Module also offers the PIOBU pins which can be used as GPIO pins.
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Note that they maintain their voltage during Backup/Self-refresh.
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required properties:
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- compatible: Should be "atmel,<chip>-secumod", "syscon".
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<chip> can be "sama5d2".
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- reg: Should contain registers location and length
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- gpio-controller: Marks the port as GPIO controller.
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- #gpio-cells: There are 2. The pin number is the
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first, the second represents additional
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parameters such as GPIO_ACTIVE_HIGH/LOW.
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secumod@fc040000 {
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compatible = "atmel,sama5d2-secumod", "syscon";
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reg = <0xfc040000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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