Dan Carpenter c8f01ffc83 drm/msm/dsi: fix off by one in dsi_bus_clk_enable error handling ... This disables a lock which wasn't enabled and it does not disable the first lock in the array. Fixes: 6e0eb52eba ("drm/msm/dsi: Parse bus clocks from a list") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211001123409.GG2283@kili Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>		2021-10-11 17:30:54 -07:00
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phy	drm/msm/dsi: dsi_phy_14nm: Take ready-bit into account in poll_for_ready	2021-10-11 17:30:53 -07:00
dsi_cfg.c	drm/msm/dsi: Fix DSI and DSI PHY regulator config from SDM660	2021-08-07 11:48:40 -07:00
dsi_cfg.h	drm/msm/dsi: rename dual DSI to bonded DSI	2021-08-07 11:48:39 -07:00
dsi_host.c	drm/msm/dsi: fix off by one in dsi_bus_clk_enable error handling	2021-10-11 17:30:54 -07:00
dsi_manager.c	drm/msm/dsi: add continuous clock support for 7nm PHY	2021-08-10 15:30:32 -07:00
dsi_phy_5nm.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi_phy_7nm.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi_phy_10nm.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi_phy_14nm.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi_phy_20nm.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi_phy_28nm_8960.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi_phy_28nm.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
dsi.c	drm/msm/dsi: Fix an error code in msm_dsi_modeset_init()	2021-10-11 17:30:53 -07:00
dsi.h	drm/msm/dsi: add continuous clock support for 7nm PHY	2021-08-10 15:30:32 -07:00
dsi.xml.h	drm/msm/dsi: add continuous clock support for 7nm PHY	2021-08-10 15:30:32 -07:00
mmss_cc.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00
sfpb.xml.h	drm/msm: Generated register update	2021-06-23 07:33:54 -07:00