Alexandre Belloni bcc5fd49a0 clk: at91: add a driver for the h32mx clock ... Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>		2014-09-22 11:38:59 +02:00
..
at91_pmc.h	clk: at91: add a driver for the h32mx clock	2014-09-22 11:38:59 +02:00
bcm2835.h
clk-conf.h	clk: Support for clock parents and rates assigned from device tree	2014-07-25 15:16:27 -07:00
mxs.h	ARM: mxs: remove custom .init_time hook	2013-09-29 21:09:34 +02:00
shmobile.h	clk: shmobile: r8a7779: Add clocks support	2014-05-12 23:07:40 -07:00
sunxi.h	clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clk	2014-05-14 16:58:21 -07:00
tegra.h	clk: tegra: remove legacy reset APIs	2013-12-11 16:45:07 -07:00
ti.h	ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)	2014-06-06 20:33:38 +03:00
zynq.h	ARM: zynq: Map I/O memory on clkc init	2014-02-10 11:21:13 +01:00