Ilya Bakoulin c31bef1cb1 drm/amd/display: Fix clock table filling logic ... [Why] Currently, the code that fills the clock table can miss filling information about some of the higher voltage states advertised by the SMU. This, in turn, may cause some of the higher pixel clock modes (e.g. 8k60) to fail validation. [How] Fill the table with one entry per DCFCLK level instead of one entry per FCLK level. This is needed because the maximum FCLK does not necessarily need maximum voltage, whereas DCFCLK values from SMU cover the full voltage range. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-05-10 18:10:49 -04:00
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amdgpu_dm	drm/amd/display: Add dc log for DP SST DSC enable/disable	2021-05-10 18:10:18 -04:00
dc	drm/amd/display: Fix clock table filling logic	2021-05-10 18:10:49 -04:00
dmub	drm/amd/display: [FW Promotion] Release 0.0.64	2021-05-10 18:06:45 -04:00
include	drm/amd/display: minor dp link training refactor	2021-05-10 18:10:42 -04:00
modules	drm/amd/display: avoid to authentication when DEVICE_COUNT=0	2021-04-28 23:35:50 -04:00
Kconfig	drm/amd/display: Support crc on specific region	2021-03-05 15:11:47 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO