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We have two bits available in the encoded page pointer to store additional information. Currently, we use one bit to request delay of the rmap removal until after a TLB flush. We want to make use of the remaining bit internally for batching of multiple pages of the same folio, specifying that the next encoded page pointer in an array is actually "nr_pages". So pass page + delay_rmap flag instead of an encoded page, to handle the encoding internally. Link: https://lkml.kernel.org/r/20240214204435.167852-6-david@redhat.com Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Hocko <mhocko@suse.com> Cc: "Naveen N. Rao" <naveen.n.rao@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: Will Deacon <will@kernel.org> Cc: Yin Fengwei <fengwei.yin@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
134 lines
4.1 KiB
C
134 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _S390_TLB_H
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#define _S390_TLB_H
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/*
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* TLB flushing on s390 is complicated. The following requirement
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* from the principles of operation is the most arduous:
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*
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* "A valid table entry must not be changed while it is attached
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* to any CPU and may be used for translation by that CPU except to
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* (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
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* or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
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* table entry, or (3) make a change by means of a COMPARE AND SWAP
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* AND PURGE instruction that purges the TLB."
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*
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* The modification of a pte of an active mm struct therefore is
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* a two step process: i) invalidate the pte, ii) store the new pte.
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* This is true for the page protection bit as well.
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* The only possible optimization is to flush at the beginning of
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* a tlb_gather_mmu cycle if the mm_struct is currently not in use.
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*
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* Pages used for the page tables is a different story. FIXME: more
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*/
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void __tlb_remove_table(void *_table);
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static inline void tlb_flush(struct mmu_gather *tlb);
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static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
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struct page *page, bool delay_rmap, int page_size);
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#define tlb_flush tlb_flush
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#define pte_free_tlb pte_free_tlb
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#define pmd_free_tlb pmd_free_tlb
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#define p4d_free_tlb p4d_free_tlb
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#define pud_free_tlb pud_free_tlb
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#include <asm/tlbflush.h>
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#include <asm-generic/tlb.h>
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/*
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* Release the page cache reference for a pte removed by
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* tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
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* has already been freed, so just do free_page_and_swap_cache.
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*
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* s390 doesn't delay rmap removal.
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*/
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static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
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struct page *page, bool delay_rmap, int page_size)
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{
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VM_WARN_ON_ONCE(delay_rmap);
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free_page_and_swap_cache(page);
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return false;
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}
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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__tlb_flush_mm_lazy(tlb->mm);
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}
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/*
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* pte_free_tlb frees a pte table and clears the CRSTE for the
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* page table from the tlb.
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*/
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static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
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unsigned long address)
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{
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__tlb_adjust_range(tlb, address, PAGE_SIZE);
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb->cleared_pmds = 1;
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if (mm_alloc_pgste(tlb->mm))
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gmap_unlink(tlb->mm, (unsigned long *)pte, address);
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tlb_remove_ptdesc(tlb, pte);
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}
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/*
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* pmd_free_tlb frees a pmd table and clears the CRSTE for the
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* segment table entry from the tlb.
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* If the mm uses a two level page table the single pmd is freed
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* as the pgd. pmd_free_tlb checks the asce_limit against 2GB
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* to avoid the double free of the pmd in this case.
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*/
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static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
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unsigned long address)
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{
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if (mm_pmd_folded(tlb->mm))
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return;
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pagetable_pmd_dtor(virt_to_ptdesc(pmd));
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__tlb_adjust_range(tlb, address, PAGE_SIZE);
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb->cleared_puds = 1;
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tlb_remove_ptdesc(tlb, pmd);
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}
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/*
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* p4d_free_tlb frees a pud table and clears the CRSTE for the
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* region second table entry from the tlb.
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* If the mm uses a four level page table the single p4d is freed
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* as the pgd. p4d_free_tlb checks the asce_limit against 8PB
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* to avoid the double free of the p4d in this case.
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*/
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static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d,
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unsigned long address)
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{
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if (mm_p4d_folded(tlb->mm))
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return;
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__tlb_adjust_range(tlb, address, PAGE_SIZE);
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb_remove_ptdesc(tlb, p4d);
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}
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/*
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* pud_free_tlb frees a pud table and clears the CRSTE for the
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* region third table entry from the tlb.
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* If the mm uses a three level page table the single pud is freed
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* as the pgd. pud_free_tlb checks the asce_limit against 4TB
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* to avoid the double free of the pud in this case.
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*/
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static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
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unsigned long address)
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{
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if (mm_pud_folded(tlb->mm))
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return;
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb->cleared_p4ds = 1;
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tlb_remove_ptdesc(tlb, pud);
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}
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#endif /* _S390_TLB_H */
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