Nuno Sa 862cf85fef iio: commom: st_sensors: ensure proper DMA alignment ... Aligning the buffer to the L1 cache is not sufficient in some platforms as they might have larger cacheline sizes for caches after L1 and thus, we can't guarantee DMA safety. That was the whole reason to introduce IIO_DMA_MINALIGN in [1]. Do the same for st_sensors common buffer. While at it, moved the odr_lock before buffer_data as we definitely don't want any other data to share a cacheline with the buffer. [1]: https://lore.kernel.org/linux-iio/20220508175712.647246-2-jic23@kernel.org/ Fixes: e031d5f558 ("iio:st_sensors: remove buffer allocation at each buffer enable") Signed-off-by: Nuno Sa <nuno.sa@analog.com> Cc: <Stable@vger.kernel.org> Link: https://lore.kernel.org/r/20240131-dev_dma_safety_stm-v2-1-580c07fae51b@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>		2024-02-04 15:01:14 +00:00
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cros_ec_sensors_core.h	iio: cros: Register FIFO callback after sensor is registered	2022-07-18 18:29:13 +01:00
inv_sensors_timestamp.h	iio: make invensense timestamp module generic	2023-07-20 19:21:28 +01:00
ssp_sensors.h
st_sensors_i2c.h
st_sensors_spi.h
st_sensors.h	iio: commom: st_sensors: ensure proper DMA alignment	2024-02-04 15:01:14 +00:00