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bda74aae20
The legacy topology detection via CPUID leaf 4, which provides the number of cores in the package and CPUID leaf 1 which provides the number of logical CPUs in case that FEATURE_HT is enabled and the CMP_LEGACY feature is not set, is shared for Intel, Centaur and Zhaoxin CPUs. Lift the code from common.c without the early detection hack and provide it as common fallback mechanism. Will be utilized in later changes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mhklinux@outlook.com> Tested-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Wang Wendy <wendy.wang@intel.com> Tested-by: K Prateek Nayak <kprateek.nayak@amd.com> Link: https://lore.kernel.org/r/20240212153624.644448852@linutronix.de
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_TOPOLOGY_H
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#define ARCH_X86_TOPOLOGY_H
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struct topo_scan {
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struct cpuinfo_x86 *c;
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unsigned int dom_shifts[TOPO_MAX_DOMAIN];
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unsigned int dom_ncpus[TOPO_MAX_DOMAIN];
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/* Legacy CPUID[1]:EBX[23:16] number of logical processors */
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unsigned int ebx1_nproc_shift;
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};
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bool topo_is_converted(struct cpuinfo_x86 *c);
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void cpu_init_topology(struct cpuinfo_x86 *c);
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void cpu_parse_topology(struct cpuinfo_x86 *c);
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void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom,
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unsigned int shift, unsigned int ncpus);
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static inline u32 topo_shift_apicid(u32 apicid, enum x86_topology_domains dom)
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{
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if (dom == TOPO_SMT_DOMAIN)
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return apicid;
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return apicid >> x86_topo_system.dom_shifts[dom - 1];
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}
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static inline u32 topo_relative_domain_id(u32 apicid, enum x86_topology_domains dom)
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{
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if (dom != TOPO_SMT_DOMAIN)
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apicid >>= x86_topo_system.dom_shifts[dom - 1];
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return apicid & (x86_topo_system.dom_size[dom] - 1);
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}
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static inline u32 topo_domain_mask(enum x86_topology_domains dom)
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{
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return (1U << x86_topo_system.dom_shifts[dom]) - 1;
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}
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#endif /* ARCH_X86_TOPOLOGY_H */
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