Conor Dooley 17e4732d1d dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible ... The l2 cache on PolarFire SoC is cross between that of the fu540 and the fu740. It has the extra interrupt from the fu740 but the lower number of cache-sets. Add a specific compatible to avoid the likes of: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Fixes: 34fc9cc3ae ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-08-31 16:57:44 +01:00
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canaan.yaml	dt-bindings: add Canaan boards compatible strings	2021-02-22 17:51:06 -08:00
cpus.yaml	dt-bindings: riscv: document cbom-block-size	2022-07-28 15:30:21 -07:00
microchip.yaml	dt-bindings: riscv: microchip: add polarberry compatible string	2022-06-01 15:28:23 -07:00
sifive-l2-cache.yaml	dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible	2022-08-31 16:57:44 +01:00
sifive.yaml	dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board	2021-01-07 17:37:41 -08:00
starfive.yaml	dt-bindings: riscv: add starfive jh7100 bindings	2021-08-04 13:25:28 -07:00