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b975b73425
Looking at hellcreek_phylink_get_caps(), I see that depending on whether is_100_mbits is set, speeds of 1G or of 100M will be advertised. The de1soc_r1_pdata sets is_100_mbits to true. The PHY modes declared in the capabilities are MII, RGMII and GMII. GMII doesn't support 100Mbps, and as for RGMII, it would be a bit implausible to me to support this PHY mode but limit it to only 25 MHz. So I've settled on MII as a phy-mode in the example, and a fixed-link of 100Mbps. As a side note, there exists such a thing as "rev-mii", because the MII protocol is asymmetric, and "mii" is the designation for the MAC side (expected to be connected to a PHY), and "rev-mii" is the designation for the PHY side (expected to be connected to a MAC). I wonder whether "mii" or "rev-mii" should actually be used here, since this is a CPU port and presumably connected to another MAC. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
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| .. | ||
| ar9331.txt | ||
| arrow,xrs700x.yaml | ||
| brcm,b53.yaml | ||
| brcm,sf2.yaml | ||
| dsa-port.yaml | ||
| dsa.txt | ||
| dsa.yaml | ||
| hirschmann,hellcreek.yaml | ||
| lan9303.txt | ||
| lantiq-gswip.txt | ||
| marvell.txt | ||
| mediatek,mt7530.yaml | ||
| microchip,ksz.yaml | ||
| microchip,lan937x.yaml | ||
| nxp,sja1105.yaml | ||
| ocelot.txt | ||
| qca8k.yaml | ||
| realtek.yaml | ||
| renesas,rzn1-a5psw.yaml | ||
| vitesse,vsc73xx.txt | ||