Huy Nguyen b973cf3245 net/mlx5e: TC: Reserved bit 31 of REG_C1 for IPsec offload ... Currently ASAP features fully utilize all the bits of the CQE's flow tag and ft_metadata field. The flow tag field cannot be used because the flow table tagging in FTE does not allow partial write. We agree to reserve bit 31 of CQE's ft_metadata for IPsec to avoid ASAP CT from dropping IPsec offloaded packet Here is the new bit layout of REG_C1. Tunnel option id is reduced to 11 bits: < IPSEC MARKER (1) | ESW_TUN_ID(12) | ESW_TUN_OPTS(11) | ESW_ZONE_ID(8) > Signed-off-by: Huy Nguyen <huyn@nvidia.com> Signed-off-by: Raed Salem <raeds@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Paul Blakey <paulb@nvidia.com>		2021-05-27 11:54:36 -07:00
..
accel.h	net/mlx5: Accel, Add core IPsec support for the Connect-X family	2020-07-16 16:36:42 -07:00
cq.h	net/mlx5: Avoid RDMA file inclusion in core driver	2020-06-27 13:50:46 -07:00
device.h	net/mlx5e: RX, Add checks for calculated Striding RQ attributes	2021-04-19 20:17:09 -07:00
doorbell.h
driver.h	RDMA merge window pull request	2021-05-01 09:15:05 -07:00
eq.h
eswitch.h	net/mlx5e: TC: Reserved bit 31 of REG_C1 for IPsec offload	2021-05-27 11:54:36 -07:00
fs_helpers.h
fs.h	net/mlx5: Treat host PF vport as other (non eswitch manager) vport	2020-11-26 18:45:03 -08:00
mlx5_ifc_fpga.h
mlx5_ifc_vdpa.h	vdpa/mlx5: Make hardware definitions visible to all mlx5 devices	2020-12-04 14:46:56 +02:00
mlx5_ifc.h	RDMA merge window pull request	2021-05-01 09:15:05 -07:00
port.h	net/mlx5: Add support for DSFP module EEPROM dumps	2021-04-11 16:34:56 -07:00
qp.h	net/mlx5: Set QP timestamp mode to default	2021-03-10 11:01:56 -08:00
rsc_dump.h	net/mlx5: Add support in query QP, CQ and MKEY segments	2020-06-23 17:26:10 +03:00
transobj.h
vport.h	net/mlx5: E-Switch, Prepare to return total vports from eswitch struct	2021-04-24 00:58:43 -07:00