Geert Uytterhoeven 6df241aace dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example ... The unit address in the example does not match the reg property. Correct the unit address to match reality. Fixes: 3e7bf4685e ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/7b93655219a6ad696dd3faa9f36fde6b094694a9.1696330005.git.geert+renesas@glider.be Signed-off-by: Rob Herring <robh@kernel.org>		2023-10-04 08:33:11 -05:00
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andestech,ax45mp-cache.yaml	dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example	2023-10-04 08:33:11 -05:00
baikal,bt1-l2-ctl.yaml
freescale-l2cache.txt
l2c2x0.yaml
marvell,feroceon-cache.txt
marvell,tauros2-cache.txt
qcom,llcc.yaml
sifive,ccache0.yaml
socionext,uniphier-system-cache.yaml