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49669da644
Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so that we can share the common parts of the SoC DTSI with the RZ/Five (RISC-V) SoC and the RZ/G2UL (ARM64) SoC. This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL (ARM64) SoC specific parts. No functional changes (same DTB). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221025220629.79321-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
28 lines
694 B
Plaintext
28 lines
694 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/*
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* DIP-Switch SW1 setting
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* 1 : High; 0: Low
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* SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
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* SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
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* Please change below macros according to SW1 setting on the SoM
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*/
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#define SW_SW0_DEV_SEL 1
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#define SW_ET0_EN_N 1
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#include "r9a07g043u.dtsi"
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#include "rzg2ul-smarc-som.dtsi"
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#include "rzg2ul-smarc.dtsi"
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/ {
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model = "Renesas SMARC EVK based on r9a07g043u11";
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compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
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};
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