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7b59e8ae92
Just like for sc7180 devices using the Chrome bootflow (AKA trogdor and IDP), sc7280 devices using the Chrome bootflow also need their firmware marked dma-coherent. On sc7280 this wasn't causing WiFi to fail to startup, since WiFi works differently there. However, on sc7280 devices we were still getting the message at bootup after commit7bd6680b47("Revert "Revert "arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()"""): qcom_scm firmware:scm: Assign memory protection call failed -22 qcom_rmtfs_mem 9c900000.memory: assign memory failed qcom_rmtfs_mem: probe of 9c900000.memory failed with error -22 We should mark SCM properly just like we did for trogdor. Fixes:7bd6680b47("Revert "Revert "arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()""") Fixes:7a1f4e7f74("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20230616081440.v2.4.I21dc14a63327bf81c6bb58fe8ed91dbdc9849ee2@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
114 lines
2.6 KiB
Plaintext
114 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sc7280 fragment for devices with Chrome bootloader
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*
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* This file mainly tries to abstract out the memory protections put into
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* place by the Chrome bootloader which are different than what's put into
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* place by Qualcomm's typical bootloader. It also has a smattering of other
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* things that will hold true for any conceivable Chrome design
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*
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* Copyright 2022 Google LLC.
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*/
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/*
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* Reserved memory changes
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*
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* Delete all unused memory nodes and define the peripheral memory regions
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* required by the setup for Chrome boards.
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*/
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/delete-node/ &hyp_mem;
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/delete-node/ &xbl_mem;
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/delete-node/ &reserved_xbl_uefi_log;
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/delete-node/ &sec_apps_mem;
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/ {
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reserved-memory {
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adsp_mem: memory@86700000 {
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reg = <0x0 0x86700000 0x0 0x2800000>;
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no-map;
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};
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camera_mem: memory@8ad00000 {
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reg = <0x0 0x8ad00000 0x0 0x500000>;
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no-map;
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};
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venus_mem: memory@8b200000 {
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reg = <0x0 0x8b200000 0x0 0x500000>;
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no-map;
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};
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wpss_mem: memory@9ae00000 {
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reg = <0x0 0x9ae00000 0x0 0x1900000>;
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no-map;
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};
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};
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};
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/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
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&pmk8350_pon {
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status = "disabled";
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};
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/*
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* Chrome designs always boot from SPI flash hooked up to the qspi.
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*
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* It's expected that all boards will support "dual SPI" at 37.5 MHz.
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* If some boards need a different speed or have a package that allows
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* Quad SPI together with WP then those boards can easily override.
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*/
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&qspi {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
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pinctrl-1 = <&qspi_sleep>;
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spi_flash: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <37500000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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&remoteproc_wpss {
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status = "okay";
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firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
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};
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&scm {
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/* TF-A firmware maps memory cached so mark dma-coherent to match. */
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dma-coherent;
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};
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&wifi {
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status = "okay";
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wifi-firmware {
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iommus = <&apps_smmu 0x1c02 0x1>;
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};
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};
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/* PINCTRL - chrome-common pinctrl */
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&tlmm {
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qspi_sleep: qspi-sleep-state {
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pins = "gpio12", "gpio13", "gpio14", "gpio15";
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/*
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* When we're not actively transferring we want pins as GPIOs
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* with output disabled so that the quad SPI IP block stops
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* driving them. We rely on the normal pulls configured in
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* the active state and don't redefine them here. Also note
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* that we don't need the reverse (output-enable) in the
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* normal mode since the "output-enable" only matters for
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* GPIO function.
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*/
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function = "gpio";
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output-disable;
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};
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};
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