mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-12-28 11:50:13 +00:00
6c1561fb90
The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for each
SoC vendor, following the same scheme that is used on arm64, mips and
riscv. This has been discussed for many years, but so far we never did
this as there was a plan to move the files out of the kernel entirely,
which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along
with their device drivers.
* The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the time.
* Amlogic C3 is a Cortex-A35 based smart IP camera chip
* Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
* Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
* Qualcomm SDX75 is the latest generation modem chip that is used
as a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
* Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie
C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those included
there are 39 new board files, but only five more 32-bit this time, probably
a new low:
* Marantec Maveo board based on dhcor imx6ull module
* Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
* Epson Moverio BT-200 AR glasses based on TI OMAP4
* PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
* ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than
we had in the recent releases:
* Three boards based on NXP i.MX8: Emtop SoM & Baseboard,
NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice
gw7905-2x device.
* NVIDIA IGX Orin and Jetson Orin Nano boards, both based on
tegra234
* Qualcomm gains support for 6 reference boards on various members
of their IPQ networking SoC series, as well as the Sony Xperia M4
Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board
on top of the various reference platforms for their new chips.
* Rockchips support for several newer boards: Indiedroid Nova (rk3588),
Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C
Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S
(rk3568)
* TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin
family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
* continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
* support for devicetree overlays on at91, bcm283x
* significant additions to existing SoC support on mediatek, qualcomm,
ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1
As usual, a lot more detail is available in the individual merge
commits.
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Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
1112 lines
26 KiB
Plaintext
1112 lines
26 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Qualcomm Technologies, Inc. IPQ8074";
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compatible = "qcom,ipq8074";
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interrupt-parent = <&intc>;
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clocks {
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bootloader@4a600000 {
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reg = <0x0 0x4a600000 0x0 0x400000>;
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no-map;
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};
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sbl@4aa00000 {
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reg = <0x0 0x4aa00000 0x0 0x100000>;
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no-map;
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};
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smem@4ab00000 {
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compatible = "qcom,smem";
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reg = <0x0 0x4ab00000 0x0 0x100000>;
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no-map;
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hwlocks = <&tcsr_mutex 0>;
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};
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memory@4ac00000 {
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reg = <0x0 0x4ac00000 0x0 0x400000>;
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no-map;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq8074", "qcom,scm";
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qcom,dload-mode = <&tcsr 0x6100>;
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};
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};
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soc: soc@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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ssphy_1: phy@58000 {
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compatible = "qcom,ipq8074-qmp-usb3-phy";
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reg = <0x00058000 0x1c4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB1_AUX_CLK>,
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<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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<&xo>;
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clock-names = "aux", "cfg_ahb", "ref";
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resets = <&gcc GCC_USB1_PHY_BCR>,
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<&gcc GCC_USB3PHY_1_PHY_BCR>;
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reset-names = "phy","common";
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status = "disabled";
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usb1_ssphy: phy@58200 {
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reg = <0x00058200 0x130>, /* Tx */
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<0x00058400 0x200>, /* Rx */
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<0x00058800 0x1f8>, /* PCS */
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<0x00058600 0x044>; /* PCS misc */
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB1_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3phy_1_cc_pipe_clk";
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};
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};
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qusb_phy_1: phy@59000 {
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compatible = "qcom,ipq8074-qusb2-phy";
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reg = <0x00059000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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<&xo>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
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status = "disabled";
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};
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ssphy_0: phy@78000 {
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compatible = "qcom,ipq8074-qmp-usb3-phy";
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reg = <0x00078000 0x1c4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB0_AUX_CLK>,
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<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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<&xo>;
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clock-names = "aux", "cfg_ahb", "ref";
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resets = <&gcc GCC_USB0_PHY_BCR>,
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<&gcc GCC_USB3PHY_0_PHY_BCR>;
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reset-names = "phy","common";
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status = "disabled";
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usb0_ssphy: phy@78200 {
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reg = <0x00078200 0x130>, /* Tx */
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<0x00078400 0x200>, /* Rx */
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<0x00078800 0x1f8>, /* PCS */
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<0x00078600 0x044>; /* PCS misc */
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3phy_0_cc_pipe_clk";
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};
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};
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qusb_phy_0: phy@79000 {
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compatible = "qcom,ipq8074-qusb2-phy";
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reg = <0x00079000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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<&xo>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
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status = "disabled";
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};
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pcie_qmp0: phy@84000 {
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compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
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reg = <0x00084000 0x1bc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE0_AUX_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>;
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clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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pcie_phy0: phy@84200 {
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reg = <0x84200 0x16c>,
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<0x84400 0x200>,
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<0x84800 0x1f0>,
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<0x84c00 0xf4>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "pcie20_phy0_pipe_clk";
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};
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};
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pcie_qmp1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x0008e000 0x1c4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE1_AUX_CLK>,
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<&gcc GCC_PCIE1_AHB_CLK>;
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clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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pcie_phy1: phy@8e200 {
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reg = <0x8e200 0x130>,
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<0x8e400 0x200>,
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<0x8e800 0x1f8>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "pcie20_phy1_pipe_clk";
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};
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};
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mdio: mdio@90000 {
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compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
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reg = <0x00090000 0x64>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_MDIO_AHB_CLK>;
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clock-names = "gcc_mdio_ahb_clk";
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status = "disabled";
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};
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qfprom: efuse@a4000 {
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compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
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reg = <0x000a4000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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prng: rng@e3000 {
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compatible = "qcom,prng-ee";
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reg = <0x000e3000 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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status = "disabled";
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};
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tsens: thermal-sensor@4a9000 {
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compatible = "qcom,ipq8074-tsens";
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reg = <0x4a9000 0x1000>, /* TM */
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<0x4a8000 0x1000>; /* SROT */
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "combined";
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#qcom,sensors = <16>;
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#thermal-sensor-cells = <1>;
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};
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cryptobam: dma-controller@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00704000 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <1>;
|
|
qcom,controlled-remotely;
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto: crypto@73a000 {
|
|
compatible = "qcom,crypto-v5.1";
|
|
reg = <0x0073a000 0x6000>;
|
|
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
|
|
<&gcc GCC_CRYPTO_AXI_CLK>,
|
|
<&gcc GCC_CRYPTO_CLK>;
|
|
clock-names = "iface", "bus", "core";
|
|
dmas = <&cryptobam 2>, <&cryptobam 3>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
tlmm: pinctrl@1000000 {
|
|
compatible = "qcom,ipq8074-pinctrl";
|
|
reg = <0x01000000 0x300000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
gpio-ranges = <&tlmm 0 0 70>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
serial_4_pins: serial4-state {
|
|
pins = "gpio23", "gpio24";
|
|
function = "blsp4_uart1";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c_0_pins: i2c-0-state {
|
|
pins = "gpio42", "gpio43";
|
|
function = "blsp1_i2c";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
|
|
spi_0_pins: spi-0-state {
|
|
pins = "gpio38", "gpio39", "gpio40", "gpio41";
|
|
function = "blsp0_spi";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
|
|
hsuart_pins: hsuart-state {
|
|
pins = "gpio46", "gpio47", "gpio48", "gpio49";
|
|
function = "blsp2_uart";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
|
|
qpic_pins: qpic-state {
|
|
pins = "gpio1", "gpio3", "gpio4",
|
|
"gpio5", "gpio6", "gpio7",
|
|
"gpio8", "gpio10", "gpio11",
|
|
"gpio12", "gpio13", "gpio14",
|
|
"gpio15", "gpio16", "gpio17";
|
|
function = "qpic";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
gcc: gcc@1800000 {
|
|
compatible = "qcom,gcc-ipq8074";
|
|
reg = <0x01800000 0x80000>;
|
|
clocks = <&xo>, <&sleep_clk>;
|
|
clock-names = "xo", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1905000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x01905000 0x20000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1937000 {
|
|
compatible = "qcom,tcsr-ipq8074", "syscon";
|
|
reg = <0x01937000 0x21000>;
|
|
};
|
|
|
|
spmi_bus: spmi@200f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0200f000 0x001000>,
|
|
<0x02400000 0x800000>,
|
|
<0x02c00000 0x800000>,
|
|
<0x03800000 0x200000>,
|
|
<0x0200a000 0x000700>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
sdhc_1: mmc@7824900 {
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x7824900 0x500>, <0x7824000 0x800>;
|
|
reg-names = "hc", "core";
|
|
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&xo>;
|
|
clock-names = "iface", "core", "xo";
|
|
resets = <&gcc GCC_SDCC1_BCR>;
|
|
max-frequency = <384000000>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
bus-width = <8>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_dma: dma-controller@7884000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x07884000 0x2b000>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
blsp1_uart1: serial@78af000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x078af000 0x200>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_uart3: serial@78b1000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x078b1000 0x200>;
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 4>,
|
|
<&blsp_dma 5>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-0 = <&hsuart_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_uart5: serial@78b3000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x078b3000 0x200>;
|
|
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
pinctrl-0 = <&serial_4_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi1: spi@78b5000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x078b5000 0x600>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-0 = <&spi_0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c2: i2c@78b6000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x078b6000 0x600>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-0 = <&i2c_0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c3: i2c@78b7000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x078b7000 0x600>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <100000>;
|
|
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c5: i2c@78b9000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x78b9000 0x600>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi5: spi@78b9000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x78b9000 0x600>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c6: i2c@78ba000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x078ba000 0x600>;
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <100000>;
|
|
dmas = <&blsp_dma 22>, <&blsp_dma 23>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qpic_bam: dma-controller@7984000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x07984000 0x1a000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qpic_nand: nand-controller@79b0000 {
|
|
compatible = "qcom,ipq8074-nand";
|
|
reg = <0x079b0000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&gcc GCC_QPIC_CLK>,
|
|
<&gcc GCC_QPIC_AHB_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&qpic_bam 0>,
|
|
<&qpic_bam 1>,
|
|
<&qpic_bam 2>;
|
|
dma-names = "tx", "rx", "cmd";
|
|
pinctrl-0 = <&qpic_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_0: usb@8af8800 {
|
|
compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
|
|
reg = <0x08af8800 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
|
<&gcc GCC_USB0_MASTER_CLK>,
|
|
<&gcc GCC_USB0_SLEEP_CLK>,
|
|
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"sleep",
|
|
"mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
|
<&gcc GCC_USB0_MASTER_CLK>,
|
|
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
assigned-clock-rates = <133330000>,
|
|
<133330000>,
|
|
<19200000>;
|
|
|
|
power-domains = <&gcc USB0_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB0_BCR>;
|
|
status = "disabled";
|
|
|
|
dwc_0: usb@8a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x8a00000 0xcd00>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&qusb_phy_0>, <&usb0_ssphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,is-utmi-l1-suspend;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
dr_mode = "host";
|
|
};
|
|
};
|
|
|
|
usb_1: usb@8cf8800 {
|
|
compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
|
|
reg = <0x08cf8800 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
|
|
<&gcc GCC_USB1_MASTER_CLK>,
|
|
<&gcc GCC_USB1_SLEEP_CLK>,
|
|
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"sleep",
|
|
"mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
|
|
<&gcc GCC_USB1_MASTER_CLK>,
|
|
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
|
|
assigned-clock-rates = <133330000>,
|
|
<133330000>,
|
|
<19200000>;
|
|
|
|
power-domains = <&gcc USB1_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB1_BCR>;
|
|
status = "disabled";
|
|
|
|
dwc_1: usb@8c00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x8c00000 0xcd00>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&qusb_phy_1>, <&usb1_ssphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,is-utmi-l1-suspend;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
dr_mode = "host";
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@b000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
|
|
ranges = <0 0xb00a000 0xffd>;
|
|
|
|
v2m@0 {
|
|
compatible = "arm,gic-v2m-frame";
|
|
msi-controller;
|
|
reg = <0x0 0xffd>;
|
|
};
|
|
};
|
|
|
|
watchdog: watchdog@b017000 {
|
|
compatible = "qcom,kpss-wdt";
|
|
reg = <0xb017000 0x1000>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&sleep_clk>;
|
|
timeout-sec = <30>;
|
|
};
|
|
|
|
apcs_glb: mailbox@b111000 {
|
|
compatible = "qcom,ipq8074-apcs-apps-global",
|
|
"qcom,ipq6018-apcs-apps-global";
|
|
reg = <0x0b111000 0x1000>;
|
|
clocks = <&a53pll>, <&xo>;
|
|
clock-names = "pll", "xo";
|
|
|
|
#clock-cells = <1>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
a53pll: clock@b116000 {
|
|
compatible = "qcom,ipq8074-a53pll";
|
|
reg = <0x0b116000 0x40>;
|
|
#clock-cells = <0>;
|
|
clocks = <&xo>;
|
|
clock-names = "xo";
|
|
};
|
|
|
|
timer@b120000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0b120000 0x1000>;
|
|
|
|
frame@b120000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b121000 0x1000>,
|
|
<0x0b122000 0x1000>;
|
|
};
|
|
|
|
frame@b123000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b123000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b124000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b124000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b125000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b125000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b126000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b126000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b127000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b127000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b128000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b128000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pcie1: pci@10000000 {
|
|
compatible = "qcom,pcie-ipq8074";
|
|
reg = <0x10000000 0xf1d>,
|
|
<0x10000f20 0xa8>,
|
|
<0x00088000 0x2000>,
|
|
<0x10100000 0x1000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
max-link-speed = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
phys = <&pcie_phy1>;
|
|
phy-names = "pciephy";
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
|
|
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
|
|
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 142
|
|
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 143
|
|
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 144
|
|
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 145
|
|
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
|
|
<&gcc GCC_PCIE1_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE1_AHB_CLK>,
|
|
<&gcc GCC_PCIE1_AUX_CLK>;
|
|
clock-names = "iface",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"aux";
|
|
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
|
<&gcc GCC_PCIE1_SLEEP_ARES>,
|
|
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
|
|
<&gcc GCC_PCIE1_AHB_ARES>,
|
|
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
|
|
reset-names = "pipe",
|
|
"sleep",
|
|
"sticky",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"axi_m_sticky";
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie0: pci@20000000 {
|
|
compatible = "qcom,pcie-ipq8074-gen3";
|
|
reg = <0x20000000 0xf1d>,
|
|
<0x20000f20 0xa8>,
|
|
<0x20001000 0x1000>,
|
|
<0x00080000 0x4000>,
|
|
<0x20100000 0x1000>;
|
|
reg-names = "dbi", "elbi", "atu", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
max-link-speed = <3>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
phys = <&pcie_phy0>;
|
|
phy-names = "pciephy";
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
|
|
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
|
|
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 75
|
|
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 78
|
|
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 79
|
|
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 83
|
|
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
|
|
<&gcc GCC_PCIE0_RCHNG_CLK>;
|
|
clock-names = "iface",
|
|
"axi_m",
|
|
"axi_s",
|
|
"axi_bridge",
|
|
"rchng";
|
|
|
|
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
|
<&gcc GCC_PCIE0_SLEEP_ARES>,
|
|
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
|
|
<&gcc GCC_PCIE0_AHB_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
|
|
reset-names = "pipe",
|
|
"sleep",
|
|
"sticky",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"axi_m_sticky",
|
|
"axi_s_sticky";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
thermal-zones {
|
|
nss-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 4>;
|
|
|
|
trips {
|
|
nss-top-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nss0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 5>;
|
|
|
|
trips {
|
|
nss-0-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nss1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 6>;
|
|
|
|
trips {
|
|
nss-1-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcss-phya0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 7>;
|
|
|
|
trips {
|
|
wcss-phya0-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcss-phya1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 8>;
|
|
|
|
trips {
|
|
wcss-phya1-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0_thermal: cpu0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 9>;
|
|
|
|
trips {
|
|
cpu0-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1_thermal: cpu1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 10>;
|
|
|
|
trips {
|
|
cpu1-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2_thermal: cpu2-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 11>;
|
|
|
|
trips {
|
|
cpu2-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3_thermal: cpu3-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 12>;
|
|
|
|
trips {
|
|
cpu3-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster_thermal: cluster-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 13>;
|
|
|
|
trips {
|
|
cluster-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcss-phyb0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 14>;
|
|
|
|
trips {
|
|
wcss-phyb0-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcss-phyb1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens 15>;
|
|
|
|
trips {
|
|
wcss-phyb1-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|