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0f554e37da
Resolve USB 3.0 gadget failure for QM and QXPB0 in super speed mode with
single IN and OUT endpoints, like mass storage devices, due to incorrect
ACTUAL_MEM_SIZE in ep_cap2 (32k instead of actual 18k). Implement dt
property cdns,on-chip-buff-size to override ep_cap2 and set it to 18k for
imx8QM and imx8QXP chips. No adverse effects for 8QXP C0.
Cc: stable@vger.kernel.org
Fixes: dce49449e0 ("usb: cdns3: allocate TX FIFO size according to composite EP number")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
308 lines
9.3 KiB
Plaintext
308 lines
9.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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conn_subsys: bus@5b000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
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conn_axi_clk: clock-conn-axi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <333333333>;
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clock-output-names = "conn_axi_clk";
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};
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conn_ahb_clk: clock-conn-ahb {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <166666666>;
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clock-output-names = "conn_ahb_clk";
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};
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conn_ipg_clk: clock-conn-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <83333333>;
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clock-output-names = "conn_ipg_clk";
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};
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usbotg1: usb@5b0d0000 {
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compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
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reg = <0x5b0d0000 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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fsl,usbphy = <&usbphy1>;
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fsl,usbmisc = <&usbmisc1 0>;
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clocks = <&usb2_lpcg 0>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x10>;
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rx-burst-size-dword = <0x10>;
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power-domains = <&pd IMX_SC_R_USB_0>;
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status = "disabled";
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};
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usbmisc1: usbmisc@5b0d0200 {
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#index-cells = <1>;
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compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
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reg = <0x5b0d0200 0x200>;
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};
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usbphy1: usbphy@5b100000 {
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compatible = "fsl,imx7ulp-usbphy";
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reg = <0x5b100000 0x1000>;
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clocks = <&usb2_lpcg 1>;
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power-domains = <&pd IMX_SC_R_USB_0_PHY>;
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status = "disabled";
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};
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usdhc1: mmc@5b010000 {
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
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<&sdhc0_lpcg IMX_LPCG_CLK_0>,
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<&sdhc0_lpcg IMX_LPCG_CLK_5>;
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clock-names = "ipg", "ahb", "per";
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power-domains = <&pd IMX_SC_R_SDHC_0>;
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status = "disabled";
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};
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usdhc2: mmc@5b020000 {
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b020000 0x10000>;
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clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
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<&sdhc1_lpcg IMX_LPCG_CLK_0>,
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<&sdhc1_lpcg IMX_LPCG_CLK_5>;
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clock-names = "ipg", "ahb", "per";
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power-domains = <&pd IMX_SC_R_SDHC_1>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step = <2>;
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status = "disabled";
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};
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usdhc3: mmc@5b030000 {
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b030000 0x10000>;
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clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
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<&sdhc2_lpcg IMX_LPCG_CLK_0>,
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<&sdhc2_lpcg IMX_LPCG_CLK_5>;
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clock-names = "ipg", "ahb", "per";
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power-domains = <&pd IMX_SC_R_SDHC_2>;
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status = "disabled";
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};
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fec1: ethernet@5b040000 {
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reg = <0x5b040000 0x10000>;
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
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<&enet0_lpcg IMX_LPCG_CLK_2>,
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<&enet0_lpcg IMX_LPCG_CLK_3>,
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<&enet0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
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assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
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assigned-clock-rates = <250000000>, <125000000>;
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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power-domains = <&pd IMX_SC_R_ENET_0>;
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status = "disabled";
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};
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fec2: ethernet@5b050000 {
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reg = <0x5b050000 0x10000>;
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
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<&enet1_lpcg IMX_LPCG_CLK_2>,
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<&enet1_lpcg IMX_LPCG_CLK_3>,
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<&enet1_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
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assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
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assigned-clock-rates = <250000000>, <125000000>;
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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power-domains = <&pd IMX_SC_R_ENET_1>;
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status = "disabled";
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};
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usbotg3: usb@5b110000 {
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compatible = "fsl,imx8qm-usb3";
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reg = <0x5b110000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
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<&usb3_lpcg IMX_LPCG_CLK_0>,
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<&usb3_lpcg IMX_LPCG_CLK_7>,
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<&usb3_lpcg IMX_LPCG_CLK_4>,
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<&usb3_lpcg IMX_LPCG_CLK_5>;
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clock-names = "lpm", "bus", "aclk", "ipg", "core";
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assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
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assigned-clock-rates = <250000000>;
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power-domains = <&pd IMX_SC_R_USB_2>;
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status = "disabled";
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usbotg3_cdns3: usb@5b120000 {
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compatible = "cdns,usb3";
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reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
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<0x5b140000 0x10000>, /* memory area for DEVICE registers */
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<0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
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reg-names = "xhci", "dev", "otg";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "host", "peripheral", "otg", "wakeup";
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phys = <&usb3_phy>;
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phy-names = "cdns3,usb3-phy";
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cdns,on-chip-buff-size = /bits/ 16 <18>;
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status = "disabled";
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};
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};
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usb3_phy: usb-phy@5b160000 {
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compatible = "nxp,salvo-phy";
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reg = <0x5b160000 0x40000>;
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clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
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clock-names = "salvo_phy_clk";
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power-domains = <&pd IMX_SC_R_USB_2_PHY>;
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#phy-cells = <0>;
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status = "disabled";
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};
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/* LPCG clocks */
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sdhc0_lpcg: clock-controller@5b200000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b200000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "sdhc0_lpcg_per_clk",
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"sdhc0_lpcg_ipg_clk",
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"sdhc0_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_0>;
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};
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sdhc1_lpcg: clock-controller@5b210000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b210000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "sdhc1_lpcg_per_clk",
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"sdhc1_lpcg_ipg_clk",
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"sdhc1_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_1>;
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};
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sdhc2_lpcg: clock-controller@5b220000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b220000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "sdhc2_lpcg_per_clk",
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"sdhc2_lpcg_ipg_clk",
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"sdhc2_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_2>;
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};
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enet0_lpcg: clock-controller@5b230000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b230000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
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clock-output-names = "enet0_lpcg_timer_clk",
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"enet0_lpcg_txc_sampling_clk",
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"enet0_lpcg_ahb_clk",
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"enet0_lpcg_rgmii_txc_clk",
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"enet0_lpcg_ipg_clk",
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"enet0_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_0>;
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};
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enet1_lpcg: clock-controller@5b240000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b240000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
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clock-output-names = "enet1_lpcg_timer_clk",
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"enet1_lpcg_txc_sampling_clk",
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"enet1_lpcg_ahb_clk",
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"enet1_lpcg_rgmii_txc_clk",
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"enet1_lpcg_ipg_clk",
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"enet1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_1>;
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};
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usb2_lpcg: clock-controller@5b270000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b270000 0x10000>;
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#clock-cells = <1>;
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clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
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clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
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power-domains = <&pd IMX_SC_R_USB_0_PHY>;
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};
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usb3_lpcg: clock-controller@5b280000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b280000 0x10000>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
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clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>,
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<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
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clock-output-names = "usb3_app_clk",
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"usb3_lpm_clk",
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"usb3_ipg_clk",
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"usb3_core_pclk",
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"usb3_phy_clk",
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"usb3_aclk";
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power-domains = <&pd IMX_SC_R_USB_2_PHY>;
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};
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};
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