Huang Rui 0d90d0ddd1 drm/amd/pm: implement processor fine grain feature for vangogh (v3) ... This patch is to implement the processor fine grain feature for vangogh. It's similar with gfx clock, the only difference is below: echo "p core_id level value" > pp_od_clk_voltage 1. "p" - set the cclk (processor) frequency 2. "core_id" - 0/1/2/3, represents which cpu core you want to select 2. "level" - 0 or 1, "0" represents the min value, "1" represents the max value 3. "value" - the target value of cclk frequency, it should be limited in the safe range v2: fix some missing changes as Evan's suggestion. v3: add version check and fix the restore. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-01-13 23:52:58 -05:00
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asic_reg	drm/amdgpu: add osssys v4_2 ip headers (v2)	2020-12-23 15:05:20 -05:00
ivsrcid	drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)	2020-06-03 13:52:03 -04:00
amd_acpi.h	drm/amd: Query and use ACPI backlight caps	2018-11-26 15:54:39 -05:00
amd_pcie_helpers.h
amd_pcie.h	drm/amdgpu: update amd_pcie.h to include gen4 speeds	2018-07-05 16:39:59 -05:00
amd_shared.h	drm/amdgpu: Add GFX Fine Grain Clock Gating flag	2020-11-04 17:08:08 -05:00
arct_ip_offset.h	drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as __maybe_unused	2020-11-24 12:09:53 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h	drm/amd/pm: correct VR shared rail info	2020-10-27 11:58:57 -04:00
atomfirmware.h	drm/amdgpu: new macro for determining 2ND_USB20PORT support	2020-12-10 16:41:49 -05:00
atomfirmwareid.h
cgs_common.h	drm/amdgpu: retire indirect mmio reg support from cgs	2020-04-09 10:43:18 -04:00
cik_structs.h	drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd	2019-05-24 12:21:01 -05:00
dimgrey_cavefish_ip_offset.h	drm/amd/include/dimgrey_cavefish_ip_offset: Mark top-level IP_BASE as __maybe_unused	2020-11-24 12:09:53 -05:00
discovery.h	drm/amdgpu/discovery: reserve discovery data at the top of VRAM	2019-10-15 15:48:46 -04:00
displayobject.h
dm_pp_interface.h	drm/amd/pp: Remove the same struct define in powerplay	2018-07-05 16:40:02 -05:00
kgd_kfd_interface.h	drm next for 5.10-rc1	2020-10-15 10:46:16 -07:00
kgd_pp_interface.h	drm/amd/pm: implement processor fine grain feature for vangogh (v3)	2021-01-13 23:52:58 -05:00
navi10_enum.h	drm/amdgpu: add navi10 enums header	2019-06-20 15:54:46 -05:00
navi10_ip_offset.h	drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unused	2020-11-24 12:09:53 -05:00
navi12_ip_offset.h	drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unused	2020-11-24 12:09:53 -05:00
navi14_ip_offset.h	drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unused	2020-11-24 12:09:53 -05:00
pptable.h
renoir_ip_offset.h	drm/amd/display: Add DCN_BASE regs	2019-10-17 16:27:27 -04:00
sienna_cichlid_ip_offset.h	drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused	2020-11-24 12:09:53 -05:00
soc15_hw_ip.h	drm/amdgpu: add navi10 ip offset header	2019-06-20 15:54:53 -05:00
soc15_ih_clientid.h	drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid	2020-06-03 13:52:04 -04:00
v9_structs.h	drm/amdkfd: Extend CU mask to 8 SEs (v3)	2019-08-02 10:19:11 -05:00
v10_structs.h	drm/amdgpu: add v10 structs header (v2)	2019-06-20 21:16:37 -05:00
vangogh_ip_offset.h	drm/amd/include/vangogh_ip_offset: Mark top-level IP_BASE as __maybe_unused	2020-11-24 12:09:53 -05:00
vega10_enum.h	drm/amdgpu: Support new arcturus mtype	2019-09-13 17:35:48 -05:00
vega10_ip_offset.h	drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused	2020-11-13 17:29:46 -05:00
vega20_ip_offset.h	drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as __maybe_unused	2020-11-24 12:09:53 -05:00
vi_structs.h	drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd	2019-05-24 12:21:01 -05:00