mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-11-23 13:05:21 +00:00
* Replace the expert mode symbols with a single helper
* Fix misuses of of_match_ptr()
* Remove partid and partname debugfs files
* tests: Fix eraseblock read speed miscalculation for lower partition sizes
* TRX parser: Allow to use on MediaTek MIPS SoCs
MTD driver changes:
* spear_smi: use GFP_KERNEL
* mchp48l640: Add SPI ID table
* mchp23k256: Add SPI ID table
* blkdevs: Avoid soft lockups with some mtd/spi devices
* aspeed-smc: Improve probe resilience
Hyperbus changes:
* HBMC_AM654 should depend on ARCH_K3
NAND core changes:
* ECC:
- Add infrastructure to support hardware engines
- Add a new helper to retrieve the ECC context
- Provide a helper to retrieve a pilelined engine device
NAND-ECC changes:
* Macronix ECC engine:
- Add Macronix external ECC engine support
- Support SPI pipelined mode
- Make two read-only arrays static const
- Fix compile test issue
Raw NAND core changes:
* Fix misuses of of_match_node()
* Rework of_get_nand_bus_width()
* Remove of_get_nand_on_flash_bbt() wrapper
* Protect access to rawnand devices while in suspend
* bindings: Document the wp-gpios property
Rax NAND controller driver changes:
* atmel: Fix refcount issue in atmel_nand_controller_init
* nandsim:
- Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
- Merge repeat codes in ns_switch_state
- Replace overflow check with kzalloc to single kcalloc
* rockchip: Fix platform_get_irq.cocci warning
* stm32_fmc2: Add NAND Write Protect support
* pl353: Set the nand chip node as the flash node
* brcmnand: Fix sparse warnings in bcma_nand
* omap_elm: Remove redundant variable 'errors'
* gpmi:
- Support fast edo timings for mx28
- Validate controller clock rate
- Fix controller timings setting
* brcmnand:
- Add BCMA shim
- BCMA controller uses command shift of 0
- Allow platform data instantation
- Add platform data structure for BCMA
- Allow working without interrupts
- Move OF operations out of brcmnand_init_cs()
- Avoid pdev in brcmnand_init_cs()
- Allow SoC to provide I/O operations
- Assign soc as early as possible
Onenand changes:
* Check for error irq
SPI-NAND core changes:
* Delay a little bit the dirmap creation
* Create direct mapping descriptors for ECC operations
SPI-NAND driver changes:
* macronix: Use random program load
SPI NOR core changes:
* Move vendor specific code out of the core into vendor drivers.
* Unify all function and object names in the vendor modules.
* Make setup() callback optional to improve readability.
* Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
declaration.
SPI changes:
* Macronix SPI controller:
- Fix the transmit path
- Create a helper to configure the controller before an operation
- Create a helper to ease the start of an operation
- Add support for direct mapping
- Add support for pipelined ECC operations
* spi-mem:
- Introduce a capability structure
- Check the controller extra capabilities
- cadence-quadspi/mxic: Provide capability structures
- Kill the spi_mem_dtr_supports_op() helper
- Add an ecc parameter to the spi_mem_op structure
Binding changes:
* Dropped mtd/cortina,gemini-flash.txt
* Convert BCM47xx partitions to json-schema
* Vendor prefixes: Clarify Macronix prefix
* SPI NAND: Convert spi-nand description file to yaml
* Raw NAND chip: Create a NAND chip description
* Raw NAND controller:
- Harmonize the property types
- Fix a comment in the examples
- Fix the reg property description
* Describe Macronix NAND ECC engine
* Macronix SPI controller:
- Document the nand-ecc-engine property
- Convert to yaml
- The interrupt property is not mandatory
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAmI7WJcACgkQJWrqGEe9
VoSzpAgAutzRv9TRUiXdBGGlJ851QaZ6ZUvT1bHKTQA+xZi+MZyNmc0cWNg3B70I
PnwyxNAmRkUQKwV5Vgy/sQrt42qZnPmr+8XMq+UiziPmgFdjiTdLqGcN619Hi12t
JqtoKL828R064LSEq5nWsJ2waoGT1nNtZK8kA2qe8ctvmH0YTThriVZUQR4/Befb
OGFheceLFycE/vkktPPr3As4603fMiyDOT7EA3Mtzgjohry0a0TqoakHCaHC/fYo
0/h+x+jJATPtgbWm1ZiV3cZ/Su00+rKuQOsiAWvM/pqDaijsVntBmtK0PRtums2Q
m8LCspuQYNnCINeQXqba9RxACpibDg==
=+6Zk
-----END PGP SIGNATURE-----
Merge tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"There has been a lot of activity in the MTD subsystem recently, with a
number of SPI-NOR cleanups as well as the introduction of ECC engines
that can be used by SPI controllers (hence a few SPI patches in here).
Core MTD changes:
- Replace the expert mode symbols with a single helper
- Fix misuses of of_match_ptr()
- Remove partid and partname debugfs files
- tests: Fix eraseblock read speed miscalculation for lower partition
sizes
- TRX parser: Allow to use on MediaTek MIPS SoCs
MTD driver changes:
- spear_smi: use GFP_KERNEL
- mchp48l640: Add SPI ID table
- mchp23k256: Add SPI ID table
- blkdevs: Avoid soft lockups with some mtd/spi devices
- aspeed-smc: Improve probe resilience
Hyperbus changes:
- HBMC_AM654 should depend on ARCH_K3
NAND core changes:
- ECC:
- Add infrastructure to support hardware engines
- Add a new helper to retrieve the ECC context
- Provide a helper to retrieve a pilelined engine device
NAND-ECC changes:
- Macronix ECC engine:
- Add Macronix external ECC engine support
- Support SPI pipelined mode
- Make two read-only arrays static const
- Fix compile test issue
Raw NAND core changes:
- Fix misuses of of_match_node()
- Rework of_get_nand_bus_width()
- Remove of_get_nand_on_flash_bbt() wrapper
- Protect access to rawnand devices while in suspend
- bindings: Document the wp-gpios property
Rax NAND controller driver changes:
- atmel: Fix refcount issue in atmel_nand_controller_init
- nandsim:
- Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
- Merge repeat codes in ns_switch_state
- Replace overflow check with kzalloc to single kcalloc
- rockchip: Fix platform_get_irq.cocci warning
- stm32_fmc2: Add NAND Write Protect support
- pl353: Set the nand chip node as the flash node
- brcmnand: Fix sparse warnings in bcma_nand
- omap_elm: Remove redundant variable 'errors'
- gpmi:
- Support fast edo timings for mx28
- Validate controller clock rate
- Fix controller timings setting
- brcmnand:
- Add BCMA shim
- BCMA controller uses command shift of 0
- Allow platform data instantation
- Add platform data structure for BCMA
- Allow working without interrupts
- Move OF operations out of brcmnand_init_cs()
- Avoid pdev in brcmnand_init_cs()
- Allow SoC to provide I/O operations
- Assign soc as early as possible
Onenand changes:
- Check for error irq
SPI-NAND core changes:
- Delay a little bit the dirmap creation
- Create direct mapping descriptors for ECC operations
SPI-NAND driver changes:
- macronix: Use random program load
SPI NOR core changes:
- Move vendor specific code out of the core into vendor drivers.
- Unify all function and object names in the vendor modules.
- Make setup() callback optional to improve readability.
- Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
declaration.
SPI changes:
- Macronix SPI controller:
- Fix the transmit path
- Create a helper to configure the controller before an operation
- Create a helper to ease the start of an operation
- Add support for direct mapping
- Add support for pipelined ECC operations
- spi-mem:
- Introduce a capability structure
- Check the controller extra capabilities
- cadence-quadspi/mxic: Provide capability structures
- Kill the spi_mem_dtr_supports_op() helper
- Add an ecc parameter to the spi_mem_op structure
Binding changes:
- Dropped mtd/cortina,gemini-flash.txt
- Convert BCM47xx partitions to json-schema
- Vendor prefixes: Clarify Macronix prefix
- SPI NAND: Convert spi-nand description file to yaml
- Raw NAND chip: Create a NAND chip description
- Raw NAND controller:
- Harmonize the property types
- Fix a comment in the examples
- Fix the reg property description
- Describe Macronix NAND ECC engine
- Macronix SPI controller:
- Document the nand-ecc-engine property
- Convert to yaml
- The interrupt property is not mandatory"
* tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits)
mtd: nand: ecc: mxic: Fix compile test issue
mtd: nand: mxic-ecc: make two read-only arrays static const
mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3
mtd: core: Remove partid and partname debugfs files
dt-bindings: mtd: partitions: convert BCM47xx to the json-schema
mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes
mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init
mtd: rawnand: rockchip: fix platform_get_irq.cocci warning
mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set
mtd: spi-nor: renumber flags
mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
mtd: spi-nor: spansion: rename vendor specific functions and defines
mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
mtd: spi-nor: move all spansion specifics into spansion.c
mtd: spi-nor: spansion: slightly rework control flow in late_init()
mtd: spi-nor: micron-st: rename vendor specific functions and defines
mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
mtd: spi-nor: move all micron-st specifics into micron-st.c
mtd: spi-nor: xilinx: correct the debug message
mtd: spi-nor: xilinx: rename vendor specific functions and defines
...
261 lines
5.8 KiB
C
261 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* mchp23k256.c
|
|
*
|
|
* Driver for Microchip 23k256 SPI RAM chips
|
|
*
|
|
* Copyright © 2016 Andrew Lunn <andrew@lunn.ch>
|
|
*/
|
|
#include <linux/device.h>
|
|
#include <linux/module.h>
|
|
#include <linux/mtd/mtd.h>
|
|
#include <linux/mtd/partitions.h>
|
|
#include <linux/mutex.h>
|
|
#include <linux/sched.h>
|
|
#include <linux/sizes.h>
|
|
#include <linux/spi/flash.h>
|
|
#include <linux/spi/spi.h>
|
|
#include <linux/of_device.h>
|
|
|
|
#define MAX_CMD_SIZE 4
|
|
|
|
struct mchp23_caps {
|
|
u8 addr_width;
|
|
unsigned int size;
|
|
};
|
|
|
|
struct mchp23k256_flash {
|
|
struct spi_device *spi;
|
|
struct mutex lock;
|
|
struct mtd_info mtd;
|
|
const struct mchp23_caps *caps;
|
|
};
|
|
|
|
#define MCHP23K256_CMD_WRITE_STATUS 0x01
|
|
#define MCHP23K256_CMD_WRITE 0x02
|
|
#define MCHP23K256_CMD_READ 0x03
|
|
#define MCHP23K256_MODE_SEQ BIT(6)
|
|
|
|
#define to_mchp23k256_flash(x) container_of(x, struct mchp23k256_flash, mtd)
|
|
|
|
static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash,
|
|
unsigned int addr, u8 *cmd)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Address is sent in big endian (MSB first) and we skip
|
|
* the first entry of the cmd array which contains the cmd
|
|
* opcode.
|
|
*/
|
|
for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8)
|
|
cmd[i] = addr;
|
|
}
|
|
|
|
static int mchp23k256_cmdsz(struct mchp23k256_flash *flash)
|
|
{
|
|
return 1 + flash->caps->addr_width;
|
|
}
|
|
|
|
static int mchp23k256_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const unsigned char *buf)
|
|
{
|
|
struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
|
|
struct spi_transfer transfer[2] = {};
|
|
struct spi_message message;
|
|
unsigned char command[MAX_CMD_SIZE];
|
|
int ret, cmd_len;
|
|
|
|
spi_message_init(&message);
|
|
|
|
cmd_len = mchp23k256_cmdsz(flash);
|
|
|
|
command[0] = MCHP23K256_CMD_WRITE;
|
|
mchp23k256_addr2cmd(flash, to, command);
|
|
|
|
transfer[0].tx_buf = command;
|
|
transfer[0].len = cmd_len;
|
|
spi_message_add_tail(&transfer[0], &message);
|
|
|
|
transfer[1].tx_buf = buf;
|
|
transfer[1].len = len;
|
|
spi_message_add_tail(&transfer[1], &message);
|
|
|
|
mutex_lock(&flash->lock);
|
|
|
|
ret = spi_sync(flash->spi, &message);
|
|
|
|
mutex_unlock(&flash->lock);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (retlen && message.actual_length > cmd_len)
|
|
*retlen += message.actual_length - cmd_len;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mchp23k256_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t *retlen, unsigned char *buf)
|
|
{
|
|
struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
|
|
struct spi_transfer transfer[2] = {};
|
|
struct spi_message message;
|
|
unsigned char command[MAX_CMD_SIZE];
|
|
int ret, cmd_len;
|
|
|
|
spi_message_init(&message);
|
|
|
|
cmd_len = mchp23k256_cmdsz(flash);
|
|
|
|
memset(&transfer, 0, sizeof(transfer));
|
|
command[0] = MCHP23K256_CMD_READ;
|
|
mchp23k256_addr2cmd(flash, from, command);
|
|
|
|
transfer[0].tx_buf = command;
|
|
transfer[0].len = cmd_len;
|
|
spi_message_add_tail(&transfer[0], &message);
|
|
|
|
transfer[1].rx_buf = buf;
|
|
transfer[1].len = len;
|
|
spi_message_add_tail(&transfer[1], &message);
|
|
|
|
mutex_lock(&flash->lock);
|
|
|
|
ret = spi_sync(flash->spi, &message);
|
|
|
|
mutex_unlock(&flash->lock);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (retlen && message.actual_length > cmd_len)
|
|
*retlen += message.actual_length - cmd_len;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set the device into sequential mode. This allows read/writes to the
|
|
* entire SRAM in a single operation
|
|
*/
|
|
static int mchp23k256_set_mode(struct spi_device *spi)
|
|
{
|
|
struct spi_transfer transfer = {};
|
|
struct spi_message message;
|
|
unsigned char command[2];
|
|
|
|
spi_message_init(&message);
|
|
|
|
command[0] = MCHP23K256_CMD_WRITE_STATUS;
|
|
command[1] = MCHP23K256_MODE_SEQ;
|
|
|
|
transfer.tx_buf = command;
|
|
transfer.len = sizeof(command);
|
|
spi_message_add_tail(&transfer, &message);
|
|
|
|
return spi_sync(spi, &message);
|
|
}
|
|
|
|
static const struct mchp23_caps mchp23k256_caps = {
|
|
.size = SZ_32K,
|
|
.addr_width = 2,
|
|
};
|
|
|
|
static const struct mchp23_caps mchp23lcv1024_caps = {
|
|
.size = SZ_128K,
|
|
.addr_width = 3,
|
|
};
|
|
|
|
static int mchp23k256_probe(struct spi_device *spi)
|
|
{
|
|
struct mchp23k256_flash *flash;
|
|
struct flash_platform_data *data;
|
|
int err;
|
|
|
|
flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
|
|
if (!flash)
|
|
return -ENOMEM;
|
|
|
|
flash->spi = spi;
|
|
mutex_init(&flash->lock);
|
|
spi_set_drvdata(spi, flash);
|
|
|
|
err = mchp23k256_set_mode(spi);
|
|
if (err)
|
|
return err;
|
|
|
|
data = dev_get_platdata(&spi->dev);
|
|
|
|
flash->caps = of_device_get_match_data(&spi->dev);
|
|
if (!flash->caps)
|
|
flash->caps = &mchp23k256_caps;
|
|
|
|
mtd_set_of_node(&flash->mtd, spi->dev.of_node);
|
|
flash->mtd.dev.parent = &spi->dev;
|
|
flash->mtd.type = MTD_RAM;
|
|
flash->mtd.flags = MTD_CAP_RAM;
|
|
flash->mtd.writesize = 1;
|
|
flash->mtd.size = flash->caps->size;
|
|
flash->mtd._read = mchp23k256_read;
|
|
flash->mtd._write = mchp23k256_write;
|
|
|
|
err = mtd_device_register(&flash->mtd, data ? data->parts : NULL,
|
|
data ? data->nr_parts : 0);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mchp23k256_remove(struct spi_device *spi)
|
|
{
|
|
struct mchp23k256_flash *flash = spi_get_drvdata(spi);
|
|
|
|
WARN_ON(mtd_device_unregister(&flash->mtd));
|
|
}
|
|
|
|
static const struct of_device_id mchp23k256_of_table[] = {
|
|
{
|
|
.compatible = "microchip,mchp23k256",
|
|
.data = &mchp23k256_caps,
|
|
},
|
|
{
|
|
.compatible = "microchip,mchp23lcv1024",
|
|
.data = &mchp23lcv1024_caps,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mchp23k256_of_table);
|
|
|
|
static const struct spi_device_id mchp23k256_spi_ids[] = {
|
|
{
|
|
.name = "mchp23k256",
|
|
.driver_data = (kernel_ulong_t)&mchp23k256_caps,
|
|
},
|
|
{
|
|
.name = "mchp23lcv1024",
|
|
.driver_data = (kernel_ulong_t)&mchp23lcv1024_caps,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, mchp23k256_spi_ids);
|
|
|
|
static struct spi_driver mchp23k256_driver = {
|
|
.driver = {
|
|
.name = "mchp23k256",
|
|
.of_match_table = mchp23k256_of_table,
|
|
},
|
|
.probe = mchp23k256_probe,
|
|
.remove = mchp23k256_remove,
|
|
.id_table = mchp23k256_spi_ids,
|
|
};
|
|
|
|
module_spi_driver(mchp23k256_driver);
|
|
|
|
MODULE_DESCRIPTION("MTD SPI driver for MCHP23K256 RAM chips");
|
|
MODULE_AUTHOR("Andrew Lunn <andre@lunn.ch>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("spi:mchp23k256");
|