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8658db0a4a
The __RISCV_INSN_FUNCS originally declared riscv_insn_is_* functions inside
the kprobes implementation. This got moved into a central header in
commit ec5f908775 ("RISC-V: Move riscv_insn_is_* macros into a common header").
Though it looks like I overlooked two of them, so fix that. FENCE itself is
an instruction defined directly by its own opcode, while the created
riscv_isn_is_system function covers all instructions defined under the SYSTEM
opcode.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20230113211955.3534431-1-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
29 lines
863 B
C
29 lines
863 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _RISCV_KERNEL_PROBES_SIMULATE_INSN_H
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#define _RISCV_KERNEL_PROBES_SIMULATE_INSN_H
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#include <asm/insn.h>
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#define RISCV_INSN_REJECTED(name, code) \
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do { \
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if (riscv_insn_is_##name(code)) { \
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return INSN_REJECTED; \
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} \
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} while (0)
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#define RISCV_INSN_SET_SIMULATE(name, code) \
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do { \
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if (riscv_insn_is_##name(code)) { \
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api->handler = simulate_##name; \
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return INSN_GOOD_NO_SLOT; \
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} \
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} while (0)
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bool simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
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#endif /* _RISCV_KERNEL_PROBES_SIMULATE_INSN_H */
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