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95207db816
include/linux/compiler-intel.h had no update in the past 3 years.
We often forget about the third C compiler to build the kernel.
For example, commit a0a12c3ed0 ("asm goto: eradicate CC_HAS_ASM_GOTO")
only mentioned GCC and Clang.
init/Kconfig defines CC_IS_GCC and CC_IS_CLANG but not CC_IS_ICC,
and nobody has reported any issue.
I guess the Intel Compiler support is broken, and nobody is caring
about it.
Harald Arnesen pointed out ICC (classic Intel C/C++ compiler) is
deprecated:
$ icc -v
icc: remark #10441: The Intel(R) C++ Compiler Classic (ICC) is
deprecated and will be removed from product release in the second half
of 2023. The Intel(R) oneAPI DPC++/C++ Compiler (ICX) is the recommended
compiler moving forward. Please transition to use this compiler. Use
'-diag-disable=10441' to disable this message.
icc version 2021.7.0 (gcc version 12.1.0 compatibility)
Arnd Bergmann provided a link to the article, "Intel C/C++ compilers
complete adoption of LLVM".
lib/zstd/common/compiler.h and lib/zstd/compress/zstd_fast.c were kept
untouched for better sync with https://github.com/facebook/zstd
Link: https://www.intel.com/content/www/us/en/developer/articles/technical/adoption-of-llvm-complete-icx.html
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Compiler-dependent intrinsics.
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*
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* Copyright (C) 2002-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*/
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#ifndef _UAPI_ASM_IA64_INTRINSICS_H
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#define _UAPI_ASM_IA64_INTRINSICS_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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/* include compiler specific intrinsics */
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#include <asm/ia64regs.h>
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#include <asm/gcc_intrin.h>
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#include <asm/cmpxchg.h>
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#define ia64_set_rr0_to_rr4(val0, val1, val2, val3, val4) \
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do { \
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ia64_set_rr(0x0000000000000000UL, (val0)); \
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ia64_set_rr(0x2000000000000000UL, (val1)); \
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ia64_set_rr(0x4000000000000000UL, (val2)); \
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ia64_set_rr(0x6000000000000000UL, (val3)); \
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ia64_set_rr(0x8000000000000000UL, (val4)); \
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} while (0)
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/*
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* Force an unresolved reference if someone tries to use
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* ia64_fetch_and_add() with a bad value.
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*/
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extern unsigned long __bad_size_for_ia64_fetch_and_add (void);
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extern unsigned long __bad_increment_for_ia64_fetch_and_add (void);
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#define IA64_FETCHADD(tmp,v,n,sz,sem) \
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({ \
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switch (sz) { \
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case 4: \
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tmp = ia64_fetchadd4_##sem((unsigned int *) v, n); \
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break; \
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\
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case 8: \
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tmp = ia64_fetchadd8_##sem((unsigned long *) v, n); \
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break; \
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\
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default: \
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__bad_size_for_ia64_fetch_and_add(); \
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} \
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})
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#define ia64_fetchadd(i,v,sem) \
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({ \
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__u64 _tmp; \
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volatile __typeof__(*(v)) *_v = (v); \
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/* Can't use a switch () here: gcc isn't always smart enough for that... */ \
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if ((i) == -16) \
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IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v)), sem); \
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else if ((i) == -8) \
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IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v)), sem); \
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else if ((i) == -4) \
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IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v)), sem); \
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else if ((i) == -1) \
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IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v)), sem); \
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else if ((i) == 1) \
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IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v)), sem); \
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else if ((i) == 4) \
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IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v)), sem); \
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else if ((i) == 8) \
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IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v)), sem); \
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else if ((i) == 16) \
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IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v)), sem); \
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else \
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_tmp = __bad_increment_for_ia64_fetch_and_add(); \
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(__typeof__(*(v))) (_tmp); /* return old value */ \
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})
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#define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */
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#endif
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#endif /* _UAPI_ASM_IA64_INTRINSICS_H */
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