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724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
170 lines
3.3 KiB
Plaintext
170 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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*/
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pwm/pwm.h>
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/ {
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aliases {
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serial0 = &uart4;
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serial1 = &usart3;
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serial2 = &uart8;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&adc {
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status = "disabled";
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};
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&dac {
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status = "disabled";
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};
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&gpiob {
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/*
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* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
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* GPIO line, however the STM32 UART driver assumes RX happens
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* during TX anyway and that it only controls drive enable DE
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* line. Hence, the RX is always enabled here.
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*/
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rs485-rx-en-hog {
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gpio-hog;
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gpios = <8 0>;
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output-low;
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line-name = "rs485-rx-en";
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};
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};
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&gpiod {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-B", "",
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"", "", "", "DRC02-Out1",
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"DRC02-Out2", "", "", "";
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};
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&gpioi {
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gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I",
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"DHCOM-R", "DHCOM-M", "", "",
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"DRC02-In2", "", "", "",
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"", "", "", "";
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/*
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* NOTE: The USB Hub on the DRC02 needs a reset signal to be
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* pulled high in order to be detected by the USB Controller.
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* This signal should be handled by USB power sequencing in
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* order to reset the Hub when USB bus is powered down, but
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* so far there is no such functionality.
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*/
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usb-hub-hog {
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gpio-hog;
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gpios = <2 0>;
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output-high;
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line-name = "usb-hub-reset";
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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/* spare dmas for other usage */
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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&i2c4 {
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touchscreen@49 {
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status = "disabled";
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};
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};
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&i2c5 { /* TP7/TP8 */
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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/* spare dmas for other usage */
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/delete-property/dmas;
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/delete-property/dma-names;
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};
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&sdmmc3 {
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/*
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* On DRC02, the SoM does not have SDIO WiFi. The pins
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* are used for on-board microSD slot instead.
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*/
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/delete-property/broken-cd;
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cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
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disable-wp;
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins_a>;
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cs-gpios = <&gpioz 3 0>;
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/* Use PIO for the display */
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "disabled"; /* Enable once there is display driver */
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/*
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* Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
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* also connected to the display board connector.
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*/
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};
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&usart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&usart3_pins_a>;
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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};
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/*
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* Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
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* however the STM32MP1 pinmux cannot map them to UART4 .
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*/
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&uart8 { /* RS485 */
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linux,rs485-enabled-at-boot-time;
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pinctrl-names = "default";
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pinctrl-0 = <&uart8_pins_a>;
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rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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};
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&usbh_ehci {
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phys = <&usbphyc_port0>;
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status = "okay";
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};
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&usbphyc {
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status = "okay";
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};
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&usbphyc_port0 {
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phy-supply = <&vdd_usb>;
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};
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&usbphyc_port1 {
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phy-supply = <&vdd_usb>;
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};
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