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The Lctech Pi F1C200s (also previously known under the Cherry Pi brand) is a small development board with the Allwinner F1C200s SoC. This is the same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM. Alongside the obligatory micro-SD card slot, the board features a SPI-NAND flash chip, LCD and touch connectors, and unpopulated expansion header pins. There are two USB Type-C ports on the board: One supplies the power, also connects to the USB MUSB OTG controller port. The other one is connected to an CH340 USB serial chip, which in turn is connected to UART1. Add a devicetree file, so that the board can be used easily. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230319212936.26649-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
331 lines
7.6 KiB
Plaintext
331 lines
7.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
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* Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
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*/
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#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
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#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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clocks {
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osc24M: clk-24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk-32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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reg = <0x0>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@1c00000 {
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compatible = "allwinner,suniv-f1c100s-system-control",
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"allwinner,sun4i-a10-system-control";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_d: sram@10000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0 {
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compatible = "allwinner,suniv-f1c100s-sram-d",
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"allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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spi0: spi@1c05000 {
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compatible = "allwinner,suniv-f1c100s-spi",
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"allwinner,sun8i-h3-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
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clock-names = "ahb", "mod";
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resets = <&ccu RST_BUS_SPI0>;
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status = "disabled";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@1c06000 {
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compatible = "allwinner,suniv-f1c100s-spi",
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"allwinner,sun8i-h3-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
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clock-names = "ahb", "mod";
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resets = <&ccu RST_BUS_SPI1>;
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status = "disabled";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,suniv-f1c100s-mmc",
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"allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>,
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<&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb", "mmc", "output", "sample";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <23>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,suniv-f1c100s-mmc",
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"allwinner,sun7i-a20-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>,
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<&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb", "mmc", "output", "sample";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <24>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@1c13000 {
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compatible = "allwinner,suniv-f1c100s-musb";
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reg = <0x01c13000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <26>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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allwinner,sram = <&otg_sram 1>;
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status = "disabled";
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};
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usbphy: phy@1c13400 {
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compatible = "allwinner,suniv-f1c100s-usb-phy";
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reg = <0x01c13400 0x10>;
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reg-names = "phy_ctrl";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb0_phy";
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resets = <&ccu RST_USB_PHY0>;
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reset-names = "usb0_reset";
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#phy-cells = <1>;
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status = "disabled";
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,suniv-f1c100s-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@1c20400 {
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compatible = "allwinner,suniv-f1c100s-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,suniv-f1c100s-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <38>, <39>, <40>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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};
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/omit-if-no-ref/
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i2c0_pd_pins: i2c0-pd-pins {
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pins = "PD0", "PD12";
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function = "i2c0";
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};
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spi0_pc_pins: spi0-pc-pins {
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pins = "PC0", "PC1", "PC2", "PC3";
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function = "spi0";
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};
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uart0_pe_pins: uart0-pe-pins {
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pins = "PE0", "PE1";
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function = "uart0";
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};
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/omit-if-no-ref/
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uart1_pa_pins: uart1-pa-pins {
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pins = "PA2", "PA3";
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function = "uart1";
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};
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};
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i2c0: i2c@1c27000 {
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compatible = "allwinner,suniv-f1c100s-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x01c27000 0x400>;
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interrupts = <7>;
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clocks = <&ccu CLK_BUS_I2C0>;
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resets = <&ccu RST_BUS_I2C0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@1c27400 {
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compatible = "allwinner,suniv-f1c100s-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x01c27400 0x400>;
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interrupts = <8>;
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clocks = <&ccu CLK_BUS_I2C1>;
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resets = <&ccu RST_BUS_I2C1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@1c27800 {
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compatible = "allwinner,suniv-f1c100s-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x01c27800 0x400>;
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interrupts = <9>;
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clocks = <&ccu CLK_BUS_I2C2>;
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resets = <&ccu RST_BUS_I2C2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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timer@1c20c00 {
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compatible = "allwinner,suniv-f1c100s-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <13>, <14>, <15>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@1c20ca0 {
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compatible = "allwinner,suniv-f1c100s-wdt",
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"allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <16>;
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clocks = <&osc32k>;
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};
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pwm: pwm@1c21000 {
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compatible = "allwinner,suniv-f1c100s-pwm",
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"allwinner,sun7i-a20-pwm";
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reg = <0x01c21000 0x400>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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ir: ir@1c22c00 {
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compatible = "allwinner,suniv-f1c100s-ir",
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"allwinner,sun6i-a31-ir";
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reg = <0x01c22c00 0x400>;
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clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
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clock-names = "apb", "ir";
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resets = <&ccu RST_BUS_IR>;
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interrupts = <6>;
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status = "disabled";
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};
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lradc: lradc@1c23400 {
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compatible = "allwinner,suniv-f1c100s-lradc",
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"allwinner,sun8i-a83t-r-lradc";
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reg = <0x01c23400 0x400>;
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interrupts = <22>;
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status = "disabled";
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};
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uart0: serial@1c25000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@1c25400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@1c25800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25800 0x400>;
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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};
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};
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