Nikola Cornij 87de6cb2f2 drm/amd/display: Reset steer fifo before unblanking the stream ... [why] During mode transition steer fifo could overflow. Quite often it recovers by itself, but sometimes it doesn't. [how] Add steer fifo reset before unblanking the stream. Also add a short delay when resetting dig resync fifo to make sure register writes don't end up back-to-back, in which case the HW might miss the reset request. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-12-05 18:19:54 -05:00
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amdgpu_dm	drm/amd/display: add default clocks if not able to fetch them	2019-11-26 12:19:08 -05:00
dc	drm/amd/display: Reset steer fifo before unblanking the stream	2019-12-05 18:19:54 -05:00
include	drm/amd/display: fixed that I2C over AUX didn't read data issue	2019-12-05 18:18:49 -05:00
modules	drm/amd/display: Only use EETF when maxCL > max display	2019-10-25 16:50:09 -04:00
Kconfig	drm/amd: Fix Kconfig indentation	2019-10-07 15:11:17 -05:00
Makefile	drm/amd/display: Add HDCP module	2019-10-03 09:10:58 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00