Martin Blumenstingl 7bcf9ef6b9 clk: meson: meson8b: Make the video clock trees mutable ... Switch from the "_ro" clock op variants to the mutable ones for all video clocks. This will allow the VPU driver to change the clocks as needed for the different video output modes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-6-martin.blumenstingl@googlemail.com		2021-09-23 11:46:38 +02:00
..
axg-aoclk.c
axg-aoclk.h
axg-audio.c	clk: meson: axg-audio: improve deferral handling	2021-05-24 10:26:27 +02:00
axg-audio.h
axg.c
axg.h
clk-cpu-dyndiv.c
clk-cpu-dyndiv.h
clk-dualdiv.c
clk-dualdiv.h
clk-mpll.c
clk-mpll.h
clk-phase.c
clk-phase.h
clk-pll.c	clk: meson: pll: switch to determine_rate for the PLL ops	2021-05-19 15:48:12 +02:00
clk-pll.h
clk-regmap.c	clk: meson: regmap: switch to determine_rate for the dividers	2021-06-30 11:37:02 -07:00
clk-regmap.h
g12a-aoclk.c
g12a-aoclk.h
g12a.c	clk: meson: g12a: Add missing NNA source clocks for g12b	2021-06-09 21:39:50 +02:00
g12a.h
gxbb-aoclk.c
gxbb-aoclk.h
gxbb.c
gxbb.h
Kconfig
Makefile
meson8-ddr.c
meson8b.c	clk: meson: meson8b: Make the video clock trees mutable	2021-09-23 11:46:38 +02:00
meson8b.h	clk: meson: meson8b: Initialize the HDMI PLL registers	2021-09-23 11:46:37 +02:00
meson-aoclk.c
meson-aoclk.h
meson-eeclk.c
meson-eeclk.h
parm.h
sclk-div.c
sclk-div.h
vid-pll-div.c
vid-pll-div.h