Swapnil Patel 2d99a7ec25 drm/amd/display: Update clock table to include highest clock setting ... [Why] Currently, the clk manager matches SocVoltage with voltage from fused settings (dfPstate clock table). And then corresponding clocks are selected. However in certain situations, this leads to clk manager not including at least one entry with highest supported clock setting. [How] Update the clk manager to include at least one entry with highest supported clock setting. Reviewed-by: Pavle Kotarac <pavle.kotarac@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-03-07 15:57:13 -05:00
..
amdgpu_dm	drm/amd/display: Extend Freesync over PCon support for more devices	2023-03-01 22:44:38 -05:00
dc	drm/amd/display: Update clock table to include highest clock setting	2023-03-07 15:57:13 -05:00
dmub	drm/amd/display: avoid unaligned access warnings	2023-02-15 22:24:56 -05:00
include	drm/amd/display: Enable Freesync over PCon	2023-01-31 14:00:44 -05:00
modules	drm/amd/display: remove unused _calculate_degamma_curve function	2023-02-15 22:24:26 -05:00
Kconfig	drm/amdgpu: Select DRM_DISPLAY_HDCP_HELPER in amdgpu	2023-02-23 17:35:58 -05:00
Makefile
TODO