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Add support for the scv instruction on POWER9 and later CPUs. For now this implements the zeroth scv vector 'scv 0', as identical to 'sc' system calls, with the exception that LR is not preserved, nor are volatile CR registers, and error is not indicated with CR0[SO], but by returning a negative errno. rfscv is implemented to return from scv type system calls. It can not be used to return from sc system calls because those are defined to preserve LR. getpid syscall throughput on POWER9 is improved by 26% (428 to 318 cycles), largely due to reducing mtmsr and mtspr. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Fix ppc64e build] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200611081203.995112-3-npiggin@gmail.com
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_POWERPC_EXCEPTION_H
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#define _ASM_POWERPC_EXCEPTION_H
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/*
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* Extracted from head_64.S
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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*
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* This file contains the low-level support and setup for the
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* PowerPC-64 platform, including trap and interrupt dispatch.
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*/
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/*
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* The following macros define the code that appears as
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* the prologue to each of the exception handlers. They
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* are split into two parts to allow a single kernel binary
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* to be used for pSeries and iSeries.
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*
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* We make as much of the exception code common between native
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* exception handlers (including pSeries LPAR) and iSeries LPAR
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* implementations as possible.
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*/
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#include <asm/feature-fixups.h>
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/* PACA save area size in u64 units (exgen, exmc, etc) */
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#define EX_SIZE 10
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/*
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* maximum recursive depth of MCE exceptions
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*/
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#define MAX_MCE_DEPTH 4
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#ifdef __ASSEMBLY__
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#define STF_ENTRY_BARRIER_SLOT \
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STF_ENTRY_BARRIER_FIXUP_SECTION; \
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nop; \
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nop; \
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nop
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#define STF_EXIT_BARRIER_SLOT \
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STF_EXIT_BARRIER_FIXUP_SECTION; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop
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/*
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* r10 must be free to use, r13 must be paca
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*/
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#define INTERRUPT_TO_KERNEL \
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STF_ENTRY_BARRIER_SLOT
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/*
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* Macros for annotating the expected destination of (h)rfid
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*
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* The nop instructions allow us to insert one or more instructions to flush the
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* L1-D cache when returning to userspace or a guest.
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*/
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#define RFI_FLUSH_SLOT \
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RFI_FLUSH_FIXUP_SECTION; \
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nop; \
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nop; \
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nop
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#define RFI_TO_KERNEL \
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rfid
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#define RFI_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define RFI_TO_USER_OR_KERNEL \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define RFI_TO_GUEST \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define HRFI_TO_KERNEL \
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hrfid
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#define HRFI_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_USER_OR_KERNEL \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_GUEST \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_UNKNOWN \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define RFSCV_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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RFSCV; \
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b rfscv_flush_fallback
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_EXCEPTION_H */
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