Jun Lei 6e17b5b8a8 drm/amd/display: update DCN2 uclk switch time ... [why] value commited to by HW team is going to be higher than pre-silicon, and will cause underflow if driver not updated [how] update hardcoded value, update pstate switching logic to fix case where with long uclk time we won't allow switch even when we should Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-22 09:34:14 -05:00
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amdgpu_dm	drm/amd/display: Rework CRTC color management	2019-06-22 09:34:13 -05:00
dc	drm/amd/display: update DCN2 uclk switch time	2019-06-22 09:34:14 -05:00
include	drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy	2019-06-22 09:34:13 -05:00
modules	drm/amd/display: Integrate color transform3x4 with 3dlut tm	2019-06-22 09:34:12 -05:00
Kconfig	drm/amd/display: enable DSC support by default	2019-06-22 09:34:08 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00