David Zhang 6bad4ff84c drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support ... [why & how] Expose vendor specific DPCD registers for rate controlling the eDP sink TCON's refresh rate during PSR active. When used in combination with PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for short. v2: Add all DPCD registers required Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-06-07 16:09:57 -04:00
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drm	drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support	2022-06-07 16:09:57 -04:00
host1x	gpu: host1x: Show all allocated syncpts via debugfs	2022-04-06 15:33:57 +02:00
ipu-v3	drm/imx: various cleanups	2022-05-06 15:07:39 +10:00
trace
vga	PCI/VGA: Move vgaarb to drivers/pci	2022-03-09 18:30:46 -06:00
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