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6b160e0513
The generic atomic.h used cmpxchg to implement the atomic
operations, it will cause daul loop to reduce the forward
guarantee. The patch implement csky custom atomic operations with
ldex/stex instructions for the best performance.
Important comment by Rutland:
8e86f0b409 ("arm64: atomics: fix use of acquire + release for
full barrier semantics")
Link: https://lore.kernel.org/linux-riscv/CAJF2gTSAxpAi=LbAdu7jntZRUa=-dJwL0VfmDfBV5MHB=rcZ-w@mail.gmail.com/T/#m27a0f1342995deae49ce1d0e1f2683f8a181d6c3
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_ATOMIC_H
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#define __ASM_CSKY_ATOMIC_H
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#ifdef CONFIG_SMP
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#include <asm-generic/atomic64.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define __atomic_acquire_fence() __bar_brarw()
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#define __atomic_release_fence() __bar_brwaw()
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static __always_inline int arch_atomic_read(const atomic_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void arch_atomic_set(atomic_t *v, int i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#define ATOMIC_OP(op) \
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static __always_inline \
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void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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__asm__ __volatile__ ( \
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"1: ldex.w %0, (%2) \n" \
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" " #op " %0, %1 \n" \
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" stex.w %0, (%2) \n" \
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" bez %0, 1b \n" \
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: "=&r" (tmp) \
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: "r" (i), "r" (&v->counter) \
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: "memory"); \
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}
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ATOMIC_OP(add)
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ATOMIC_OP(sub)
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ATOMIC_OP(and)
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ATOMIC_OP( or)
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ATOMIC_OP(xor)
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#undef ATOMIC_OP
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#define ATOMIC_FETCH_OP(op) \
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static __always_inline \
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int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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register int ret, tmp; \
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__asm__ __volatile__ ( \
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"1: ldex.w %0, (%3) \n" \
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" mov %1, %0 \n" \
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" " #op " %0, %2 \n" \
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" stex.w %0, (%3) \n" \
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" bez %0, 1b \n" \
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: "=&r" (tmp), "=&r" (ret) \
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: "r" (i), "r"(&v->counter) \
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: "memory"); \
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return ret; \
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}
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#define ATOMIC_OP_RETURN(op, c_op) \
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static __always_inline \
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int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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return arch_atomic_fetch_##op##_relaxed(i, v) c_op i; \
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}
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#define ATOMIC_OPS(op, c_op) \
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ATOMIC_FETCH_OP(op) \
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ATOMIC_OP_RETURN(op, c_op)
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ATOMIC_OPS(add, +)
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ATOMIC_OPS(sub, -)
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#define ATOMIC_OPS(op) \
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ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(and)
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ATOMIC_OPS( or)
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ATOMIC_OPS(xor)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#define ATOMIC_OP() \
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static __always_inline \
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int arch_atomic_xchg_relaxed(atomic_t *v, int n) \
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{ \
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return __xchg_relaxed(n, &(v->counter), 4); \
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} \
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static __always_inline \
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int arch_atomic_cmpxchg_relaxed(atomic_t *v, int o, int n) \
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{ \
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return __cmpxchg_relaxed(&(v->counter), o, n, 4); \
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} \
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static __always_inline \
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int arch_atomic_cmpxchg_acquire(atomic_t *v, int o, int n) \
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{ \
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return __cmpxchg_acquire(&(v->counter), o, n, 4); \
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} \
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static __always_inline \
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int arch_atomic_cmpxchg(atomic_t *v, int o, int n) \
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{ \
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return __cmpxchg(&(v->counter), o, n, 4); \
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}
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#define ATOMIC_OPS() \
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ATOMIC_OP()
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ATOMIC_OPS()
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#define arch_atomic_xchg_relaxed arch_atomic_xchg_relaxed
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#define arch_atomic_cmpxchg_relaxed arch_atomic_cmpxchg_relaxed
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#define arch_atomic_cmpxchg_acquire arch_atomic_cmpxchg_acquire
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#define arch_atomic_cmpxchg arch_atomic_cmpxchg
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#undef ATOMIC_OPS
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#undef ATOMIC_OP
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#else
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#include <asm-generic/atomic.h>
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#endif
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#endif /* __ASM_CSKY_ATOMIC_H */
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