Wayne Lin 660d540640 drm/amd/display: Fix vertical interrupt 0 registering issue ... [Why] Find out that when we are registering vertical interrupt0, we get DC_IRQ_SOURCE_INVALID when call dc_interrupt_to_irq_source for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL. After analyzing, it's due to the defined value for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL is not (DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL + 1). It's not incremental sequence. [How] Use an array to record all vertical interrupt0 SRCID. While registering interrupt, use an incremental index to visit the array to get the right SRCID to register. Also add error handling to avoid potential pointer problem. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-03-23 23:36:27 -04:00
..
acp	drm: amd/acp: fix broken menu structure	2020-03-13 11:52:35 -04:00
amdgpu	drm/amdgpu/display: re-enable freesync video patches	2021-03-23 23:36:10 -04:00
amdkfd	drm/amdkfd: fix build error with AMD_IOMMU_V2=m	2021-03-23 23:28:11 -04:00
display	drm/amd/display: Fix vertical interrupt 0 registering issue	2021-03-23 23:36:27 -04:00
include	drm/amd/pm: add a new sysfs entry for default power limit	2021-03-23 23:30:55 -04:00
pm	drm/amd/pm: correct the gpu metrics version	2021-03-23 23:36:20 -04:00