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61af6e22ec
On Amlogic G12A SoC, the 2,97GHz PLL frequency is not stable enough to provide a correct 297MHz pixel clock, so switch the PLL base frequency with a /2 OD when the 297MHz pixel clock is requested. This solves the issue on G12A and also works fine on GXBB, GXL & GXM. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-2-narmstrong@baylibre.com |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| meson_crtc.c | ||
| meson_crtc.h | ||
| meson_drv.c | ||
| meson_drv.h | ||
| meson_dw_hdmi.c | ||
| meson_dw_hdmi.h | ||
| meson_overlay.c | ||
| meson_overlay.h | ||
| meson_plane.c | ||
| meson_plane.h | ||
| meson_registers.h | ||
| meson_vclk.c | ||
| meson_vclk.h | ||
| meson_venc_cvbs.c | ||
| meson_venc_cvbs.h | ||
| meson_venc.c | ||
| meson_venc.h | ||
| meson_viu.c | ||
| meson_viu.h | ||
| meson_vpp.c | ||
| meson_vpp.h | ||