Wenjing Liu 613a819955 drm/amd/display: fix a pipe mapping error in dcn32_fpu ... [why] In dcn32 DML pipes are ordered the same as dc pipes but only for used pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices would be 0 and 1 respectively. However update_pipe_slice_table_with_split_flags doesn't skip indices for free pipes. This causes us to not reference correct dml pipe output when building pipe topology. [how] Use two variables to iterate dc and dml pipes respectively and only increment dml pipe index when current dc pipe is not free. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-11-29 16:48:58 -05:00
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drm	drm/amd/display: fix a pipe mapping error in dcn32_fpu	2023-11-29 16:48:58 -05:00
host1x	gpu: host1x: Correct allocated size for contexts	2023-10-11 22:52:44 +02:00
ipu-v3	drm for 6.6-rc1	2023-08-30 13:34:34 -07:00
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