Hansen 5a1fef0278 drm/amd/display: Fix detection of 4 lane for DPALT ... [Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2021-10-06 16:14:17 -04:00
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drm	drm/amd/display: Fix detection of 4 lane for DPALT	2021-10-06 16:14:17 -04:00
host1x	gpu: host1x: Plug potential memory leak	2021-09-16 18:06:52 +02:00
ipu-v3	Updates to the interrupt core and driver subsystems:	2021-08-30 14:38:37 -07:00
trace
vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
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